spinal.core

PhaseVhdl

Related Doc: package core

class PhaseVhdl extends PhaseMisc with VhdlBase

Created by PIC32F_USER on 05/06/2016.

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  1. PhaseVhdl
  2. VhdlBase
  3. VhdlVerilogBase
  4. PhaseMisc
  5. Phase
  6. AnyRef
  7. Any
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Instance Constructors

  1. new PhaseVhdl(pc: PhaseContext)

Type Members

  1. class Process extends AnyRef

    Definition Classes
    VhdlVerilogBase
  2. case class WrappedStuff(originalName: String, newName: String) extends Product with Serializable

Value Members

  1. final def !=(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any
  2. final def ##(): Int

    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any
  4. final def asInstanceOf[T0]: T0

    Definition Classes
    Any
  5. def blackBoxRemplaceULogic(b: BlackBox, str: String): String

  6. def clone(): AnyRef

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  7. def compile(component: Component): Unit

  8. def emit(component: Component): String

  9. def emitArchitecture(component: Component, builder: ComponentBuilder): Unit

  10. def emitAssignedReference(node: Node): String

    Definition Classes
    VhdlBase
  11. def emitAssignement(to: Node, from: Node, ret: StringBuilder, tab: String, assignementKind: String): Unit

  12. def emitAssignementLevel(context: AssignementLevel, ret: StringBuilder, tab: String, assignementKind: String, isElseIf: Boolean = false, hiddenSensitivity: Set[Node] = null): Unit

  13. def emitAsyncronous(component: Component, ret: StringBuilder, funcRet: StringBuilder): Unit

  14. def emitAttributes(node: Node, attributes: Iterable[Attribute], vhdlType: String, ret: StringBuilder, postfix: String = ""): Unit

  15. def emitAttributesDef(component: Component, ret: StringBuilder): Unit

  16. def emitBlackBoxComponent(component: BlackBox, ret: StringBuilder): Unit

  17. def emitBlackBoxComponents(component: Component, ret: StringBuilder): Unit

  18. def emitClockEdge(clock: Bool, edgeKind: EdgeKind): String

    Definition Classes
    VhdlBase
  19. def emitComponentInstances(component: Component, ret: StringBuilder): Unit

  20. def emitDataType(node: Node, constrained: Boolean = true): String

    Definition Classes
    VhdlBase
  21. def emitDebug(component: Component, ret: StringBuilder, enumDebugSignals: ArrayBuffer[SpinalEnumCraft[_]]): Unit

  22. def emitDirection(baseType: BaseType): String

    Definition Classes
    VhdlBase
  23. def emitEntity(component: Component, builder: ComponentBuilder): Unit

  24. def emitEnumLiteral[T <: SpinalEnum](enum: SpinalEnumElement[T], encoding: SpinalEnumEncoding): String

    Definition Classes
    VhdlBase
  25. def emitEnumPackage(out: FileWriter): Unit

  26. def emitEnumType(enum: SpinalEnum, encoding: SpinalEnumEncoding): String

    Definition Classes
    VhdlBase
  27. def emitEnumType[T <: SpinalEnum](enum: SpinalEnumCraft[T]): String

    Definition Classes
    VhdlBase
  28. def emitFuncDef(funcName: String, node: Node, context: AssignementLevel): StringBuilder

  29. def emitLibrary(builder: ComponentBuilder): Unit

  30. def emitLibrary(ret: StringBuilder): Unit

    Definition Classes
    VhdlBase
  31. def emitLogic(node: Node): String

  32. def emitPackage(out: FileWriter): Unit

  33. def emitRange(node: Widthable): String

    Definition Classes
    VhdlBase
  34. def emitReference(node: Node): String

    Definition Classes
    VhdlBase
  35. def emitSignal(ref: Node, typeNode: Node): String

    Definition Classes
    VhdlBase
  36. def emitSignals(component: Component, ret: StringBuilder, enumDebugSignals: ArrayBuffer[SpinalEnumCraft[_]]): Unit

  37. def emitSyncronous(component: Component, ret: StringBuilder): Unit

  38. def emitWrappedIoConnection(buff: StringBuilder, map: HashMap[BaseType, WrappedStuff]): Unit

  39. def emitWrappedIoSignals(buff: StringBuilder, map: HashMap[BaseType, WrappedStuff]): Unit

  40. val emitedComponent: Map[ComponentBuilder, ComponentBuilder]

  41. val emitedComponentRef: Map[Component, Component]

  42. def enumEgualsImpl(eguals: Boolean)(op: Modifier): String

  43. var enumPackageName: String

    Definition Classes
    VhdlBase
  44. final def eq(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef
  45. def equals(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any
  46. def extractBitVectorFixed(func: Modifier): String

  47. def extractBitVectorFloating(func: Modifier): String

  48. def extractBoolFixed(func: Modifier): String

  49. def extractBoolFloating(func: Modifier): String

  50. def finalize(): Unit

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  51. def getAsyncProcesses(component: Component, merge: Boolean = true): Seq[Process]

    Definition Classes
    VhdlVerilogBase
  52. def getBaseTypeSignalInitialisation(signal: BaseType): String

  53. final def getClass(): Class[_]

    Definition Classes
    AnyRef → Any
  54. def getEnumDebugType(spinalEnum: SpinalEnum): String

  55. def getEnumToDebugFuntion(spinalEnum: SpinalEnum, source: SpinalEnumEncoding): String

  56. def getReEncodingFuntion(spinalEnum: SpinalEnum, source: SpinalEnumEncoding, target: SpinalEnumEncoding): String

  57. def getSensitivity(nodes: Iterable[Node], includeNodes: Boolean): Set[Node]

    Definition Classes
    VhdlVerilogBase
  58. def hasNetlistImpact: Boolean

    Definition Classes
    PhaseMiscPhase
  59. def hashCode(): Int

    Definition Classes
    AnyRef → Any
  60. def impl(pc: PhaseContext): Unit

    Definition Classes
    PhaseVhdlPhase
  61. def ioStdLogicVectorRestoreNames(map: HashMap[BaseType, WrappedStuff]): Unit

  62. def ioStdLogicVectorWrapNames(): HashMap[BaseType, WrappedStuff]

  63. final def isInstanceOf[T0]: Boolean

    Definition Classes
    Any
  64. def isReferenceable(node: Node): Boolean

    Definition Classes
    VhdlVerilogBase
  65. var memBitsMaskKind: MemBitsMaskKind

  66. val modifierImplMap: Map[String, (Modifier) ⇒ String]

  67. def moduloImpl(op: Modifier): String

  68. final def ne(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef
  69. final def notify(): Unit

    Definition Classes
    AnyRef
  70. final def notifyAll(): Unit

    Definition Classes
    AnyRef
  71. val opThatNeedBoolCast: Set[String]

  72. def opThatNeedBoolCastGen(a: String, b: String): List[String]

  73. def operatorImplAsBinaryOperator(vhd: String)(op: Modifier): String

  74. def operatorImplAsBitsToEnum(func: Modifier): String

  75. def operatorImplAsEnumToBits(func: Modifier): String

  76. def operatorImplAsEnumToEnum(func: Modifier): String

  77. def operatorImplAsFunction(vhd: String)(func: Modifier): String

  78. def operatorImplAsUnaryOperator(vhd: String)(op: Modifier): String

  79. var outFile: FileWriter

  80. var packageName: String

    Definition Classes
    VhdlBase
  81. var referenceSet: Set[Node with Nameable with ContextUser]

    Definition Classes
    VhdlBase
  82. def resizeFunction(vhdlFunc: String)(func: Modifier): String

  83. def shiftLeftBitsByIntFixedWidthImpl(func: Modifier): String

  84. def shiftLeftBitsByUIntFixedWidthImpl(func: Modifier): String

  85. def shiftLeftByIntFixedWidthImpl(func: Modifier): String

  86. def shiftLeftByIntImpl(func: Modifier): String

  87. def shiftLeftByUIntFixedWidthImpl(func: Modifier): String

  88. def shiftRightBitsByIntFixedWidthImpl(func: Modifier): String

  89. def shiftRightByIntFixedWidthImpl(func: Modifier): String

  90. def shiftRightByIntImpl(func: Modifier): String

  91. final def synchronized[T0](arg0: ⇒ T0): T0

    Definition Classes
    AnyRef
  92. def toSpinalEnumCraft[T <: SpinalEnum](that: Any): SpinalEnumCraft[T]

  93. def toString(): String

    Definition Classes
    AnyRef → Any
  94. def unaryAllBy(cast: String)(func: Modifier): String

  95. def useNodeConsumers: Boolean

    Definition Classes
    PhaseVhdlPhase
  96. final def wait(): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  97. final def wait(arg0: Long, arg1: Int): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  98. final def wait(arg0: Long): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Inherited from VhdlBase

Inherited from VhdlVerilogBase

Inherited from PhaseMisc

Inherited from Phase

Inherited from AnyRef

Inherited from Any

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