spinal.core

VhdlTestBenchBackend

Related Doc: package core

class VhdlTestBenchBackend extends VhdlBase with PhaseMisc

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  1. VhdlTestBenchBackend
  2. PhaseMisc
  3. Phase
  4. VhdlBase
  5. VhdlVerilogBase
  6. AnyRef
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Instance Constructors

  1. new VhdlTestBenchBackend(pc: PhaseContext)

Type Members

  1. class Process extends AnyRef

    Definition Classes
    VhdlVerilogBase

Value Members

  1. final def !=(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any
  2. final def ##(): Int

    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any
  4. final def asInstanceOf[T0]: T0

    Definition Classes
    Any
  5. def clone(): AnyRef

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  6. def emitAssignedReference(node: Node): String

    Definition Classes
    VhdlBase
  7. def emitClockEdge(clock: Bool, edgeKind: EdgeKind): String

    Definition Classes
    VhdlBase
  8. def emitComponentInstance(c: Component, ret: StringBuilder): Unit

  9. def emitDataType(node: Node, constrained: Boolean = true): String

    Definition Classes
    VhdlBase
  10. def emitDirection(baseType: BaseType): String

    Definition Classes
    VhdlBase
  11. def emitEnumLiteral[T <: SpinalEnum](enum: SpinalEnumElement[T], encoding: SpinalEnumEncoding): String

    Definition Classes
    VhdlBase
  12. def emitEnumType(enum: SpinalEnum, encoding: SpinalEnumEncoding): String

    Definition Classes
    VhdlBase
  13. def emitEnumType[T <: SpinalEnum](enum: SpinalEnumCraft[T]): String

    Definition Classes
    VhdlBase
  14. def emitLibrary(ret: StringBuilder): Unit

    Definition Classes
    VhdlBase
  15. def emitRange(node: Widthable): String

    Definition Classes
    VhdlBase
  16. def emitReference(node: Node): String

    Definition Classes
    VhdlBase
  17. def emitSignal(ref: Node, typeNode: Node): String

    Definition Classes
    VhdlBase
  18. def emitSignals(c: Component, ret: StringBuilder): Unit

  19. def emitUserCode(tab: String, name: String, ret: StringBuilder): Unit

  20. var enumPackageName: String

    Definition Classes
    VhdlBase
  21. final def eq(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef
  22. def equals(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any
  23. def extractUserCodes: Unit

  24. def finalize(): Unit

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  25. def getAsyncProcesses(component: Component, merge: Boolean = true): Seq[Process]

    Definition Classes
    VhdlVerilogBase
  26. final def getClass(): Class[_]

    Definition Classes
    AnyRef → Any
  27. def getSensitivity(nodes: Iterable[Node], includeNodes: Boolean): Set[Node]

    Definition Classes
    VhdlVerilogBase
  28. def hasNetlistImpact: Boolean

    Definition Classes
    PhaseMiscPhase
  29. def hashCode(): Int

    Definition Classes
    AnyRef → Any
  30. def impl(pc: PhaseContext): Unit

    Definition Classes
    VhdlTestBenchBackendPhase
  31. final def isInstanceOf[T0]: Boolean

    Definition Classes
    Any
  32. def isReferenceable(node: Node): Boolean

    Definition Classes
    VhdlVerilogBase
  33. final def ne(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef
  34. final def notify(): Unit

    Definition Classes
    AnyRef
  35. final def notifyAll(): Unit

    Definition Classes
    AnyRef
  36. var out: FileWriter

  37. def outputFilePath: String

  38. var packageName: String

    Definition Classes
    VhdlBase
  39. var referenceSet: Set[Node with Nameable with ContextUser]

    Definition Classes
    VhdlBase
  40. final def synchronized[T0](arg0: ⇒ T0): T0

    Definition Classes
    AnyRef
  41. var tbName: String

  42. def toString(): String

    Definition Classes
    AnyRef → Any
  43. def useNodeConsumers: Boolean

    Definition Classes
    VhdlTestBenchBackendPhase
  44. val userCodes: Map[String, String]

  45. final def wait(): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  46. final def wait(arg0: Long, arg1: Int): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  47. final def wait(arg0: Long): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Inherited from PhaseMisc

Inherited from Phase

Inherited from VhdlBase

Inherited from VhdlVerilogBase

Inherited from AnyRef

Inherited from Any

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