spinal.core.internals

ComponentEmiter

Related Doc: package internals

abstract class ComponentEmiter extends AnyRef

Linear Supertypes
AnyRef, Any
Known Subclasses
ComponentEmiterVerilog, ComponentEmiterVhdl
Ordering
  1. Alphabetic
  2. By inheritance
Inherited
  1. ComponentEmiter
  2. AnyRef
  3. Any
  1. Hide All
  2. Show all
Learn more about member selection
Visibility
  1. Public
  2. All

Instance Constructors

  1. new ComponentEmiter()

Type Members

  1. class AsyncProcess extends AnyRef

  2. class SyncGroup extends AnyRef

Abstract Value Members

  1. abstract def algoIdIncrementalBase: Int

  2. abstract def component: Component

  3. abstract def mergeAsyncProcess: Boolean

  4. abstract def wrapSubInput(io: BaseType): Unit

Concrete Value Members

  1. final def !=(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any

  2. final def ##(): Int

    Definition Classes
    AnyRef → Any

  3. final def ==(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any

  4. var algoIdIncrementalOffset: Int

  5. def allocateAlgoIncrementale(): Int

  6. val analogs: ArrayBuffer[BaseType]

  7. final def asInstanceOf[T0]: T0

    Definition Classes
    Any

  8. def clone(): AnyRef

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  9. def elaborate(): Unit

  10. final def eq(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  11. def equals(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any

  12. val expressionToWrap: LinkedHashSet[Expression]

  13. def finalize(): Unit

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )

  14. final def getClass(): Class[_]

    Definition Classes
    AnyRef → Any

  15. def getOrDefault[X, Y](map: ConcurrentHashMap[X, Y], key: X, default: Y): Y

  16. def hashCode(): Int

    Definition Classes
    AnyRef → Any

  17. final def isInstanceOf[T0]: Boolean

    Definition Classes
    Any

  18. def isSubComponentInputBinded(data: BaseType): BaseType

  19. val mems: ArrayBuffer[Mem[_]]

  20. val multiplexersPerSelect: LinkedHashMap[(Expression with WidthProvider, Int), ArrayBuffer[Multiplexer]]

  21. final def ne(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  22. final def notify(): Unit

    Definition Classes
    AnyRef

  23. final def notifyAll(): Unit

    Definition Classes
    AnyRef

  24. val openSubIo: HashSet[BaseType]

  25. val outputsToBufferize: LinkedHashSet[BaseType]

  26. val processes: LinkedHashSet[AsyncProcess]

  27. val referencesOverrides: HashMap[Nameable, Any]

  28. val subComponentInputToNotBufferize: HashSet[Any]

  29. val syncGroups: LinkedHashMap[(ClockDomain, ScopeStatement, Boolean), SyncGroup]

  30. final def synchronized[T0](arg0: ⇒ T0): T0

    Definition Classes
    AnyRef

  31. def toString(): String

    Definition Classes
    AnyRef → Any

  32. final def wait(): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  33. final def wait(arg0: Long, arg1: Int): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  34. final def wait(arg0: Long): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  35. val wrappedExpressionToName: HashMap[Expression, String]

Inherited from AnyRef

Inherited from Any

Ungrouped