class
VhdlBackend extends Backend with VhdlBase
Instance Constructors
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new
VhdlBackend()
Type Members
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class
WhenTree extends AnyRef
Value Members
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final
def
!=(arg0: Any): Boolean
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final
def
##(): Int
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final
def
==(arg0: Any): Boolean
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def
addComponent(c: Component): Unit
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def
addInOutBinding: Unit
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def
addNodesIntoComponent: Unit
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def
addReservedKeyWordToScope(scope: Scope): Unit
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def
allocateNames: Unit
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def
allowLiteralToCrossHierarchy: Unit
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def
allowNodesToReadInputOfKindComponent: Unit
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def
allowNodesToReadOutputs: Unit
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final
def
asInstanceOf[T0]: T0
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def
blackBoxRemplaceULogic(b: BlackBox, str: String): String
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def
checkCombinationalLoops: Unit
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def
checkCrossClockDomains: Unit
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def
checkInferedWidth: Unit
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def
check_noAsyncNodeWithIncompletAssignment: Unit
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def
check_noNull_noCrossHierarchy_noInputRegister_noDirectionLessIo: Unit
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def
clone(): AnyRef
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def
collectAndNameEnum: Unit
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def
compile(component: Component): Unit
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val
components: ArrayBuffer[Component]
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def
deleteUselessBaseTypes: Unit
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def
dontSymplifyBasetypeWithComplexAssignement: Unit
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def
emit(component: Component): String
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def
emitAssignement(to: Node, from: Node, ret: StringBuilder, tab: String, assignementKind: String): Unit
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def
emitAsyncronous(component: Component, ret: StringBuilder, funcRet: StringBuilder): Unit
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def
emitAttributes(node: Node, vhdlType: String, ret: StringBuilder): Unit
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def
emitAttributesDef(component: Component, ret: StringBuilder): Unit
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def
emitBlackBoxComponent(component: BlackBox, ret: StringBuilder): Unit
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def
emitBlackBoxComponents(component: Component, ret: StringBuilder): Unit
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def
emitClockEdge(clock: Bool, edgeKind: EdgeKind): String
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def
emitComponentInstances(component: Component, ret: StringBuilder): Unit
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def
emitDataType(node: Node, constrained: Boolean = true): String
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def
emitDirection(baseType: BaseType): String
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def
emitEntityName(component: Component): Unit
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def
emitEnumPackage(out: FileWriter): Unit
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def
emitFuncDef(funcName: String, node: Node, context: AssignementLevel): StringBuilder
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def
emitLibrary(ret: StringBuilder): Unit
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def
emitLogic(node: Node): String
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def
emitPackage(out: FileWriter): Unit
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def
emitRange(node: Node): String
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def
emitReference(node: Node): String
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def
emitSignal(ref: Node, typeNode: Node): String
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def
emitSignals(component: Component, ret: StringBuilder): Unit
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def
emitSyncronous(component: Component, ret: StringBuilder): Unit
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var
enumPackageName: String
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final
def
eq(arg0: AnyRef): Boolean
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def
equals(arg0: Any): Boolean
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def
extractBitVectorFixed(func: Modifier): String
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def
extractBitVectorFloating(func: Modifier): String
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def
extractBoolFixed(func: Modifier): String
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def
extractBoolFloating(func: Modifier): String
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def
fillNodeConsumer: Unit
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def
finalize(): Unit
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var
forceMemToBlackboxTranslation: Boolean
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final
def
getClass(): Class[_]
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def
getSensitivity(nodes: Iterable[Node], includeNodes: Boolean): Set[Node]
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val
globalScope: Scope
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def
hashCode(): Int
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def
inferWidth: Unit
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final
def
isInstanceOf[T0]: Boolean
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def
isReferenceable(node: Node): Boolean
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var
jsonReportPath: String
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var
library: String
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val
modifierImplMap: Map[String, (Modifier) ⇒ String]
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def
nameBinding: Unit
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def
nameComponentDeclaration(c: Component): Unit
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def
nameNodesByReflection(): Unit
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final
def
ne(arg0: AnyRef): Boolean
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def
normalizeNodeInputs: Unit
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final
def
notify(): Unit
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final
def
notifyAll(): Unit
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val
opThatNeedBoolCast: Set[String]
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def
opThatNeedBoolCastGen(a: String, b: String): List[String]
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def
operatorImplAsBitsToEnum(func: Modifier): String
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def
operatorImplAsFunction(vhd: String)(func: Modifier): String
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def
operatorImplAsOperator(vhd: String)(op: Modifier): String
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def
orderComponentsNodes: Unit
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var
out: FileWriter
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var
outputFile: String
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var
packageName: String
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def
printStates: Unit
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def
propagateBaseTypeWidth: Unit
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def
pullClockDomains: Unit
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def
removeComponentThatNeedNoHdlEmit: ArrayBuffer[Component]
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def
removeNodeConsumer: Unit
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def
remplaceMemByBlackBox_simplifyWriteReadWithSameAddress: Unit
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val
reservedKeyWords: Set[String]
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def
simplifyBlacBoxGenerics: Unit
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def
simplifyNodes: Unit
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var
sortedComponents: ArrayBuffer[Component]
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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def
toString(): String
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val
vhdlKeyWords: Set[String]
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final
def
wait(): Unit
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
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def
walkNodes(walker: (Node, Stack[Node]) ⇒ Unit, nodeStack: Stack[Node] = walkNodesDefautStack): Unit
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def
walkNodes2(walker: (Node) ⇒ Unit, nodeStack: Stack[Node] = walkNodesDefautStack): Unit
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def
walkNodesBlackBoxGenerics: Stack[Node]
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def
walkNodesDefautStack: Stack[Node]
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def
walker_addInOutBinding(node: Node, stack: Stack[Node]): Unit
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def
walker_deleteUselessBaseTypes(node: Node, stack: Stack[Node]): Unit
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def
walker_matchWidth(node: Node, stack: Stack[Node]): Unit
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def
walker_nodeConsumer(node: Node, stack: Stack[Node]): Unit
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def
walker_pullClockDomains(node: Node, stack: Stack[Node]): Unit
Inherited from AnyRef
Inherited from Any
Created by PIC18F on 07.01.2015.