BitVector
Related Doc:
package core
Used to know the data type of the children class of BitVector
Return a range of bits at offset and of width bitCount
Return a range of bits at offset and of width bitCount
val myBool = myBits(myUInt, 2 bits)
Return a range of bits at offset and of width bitCount
Return a range of bits at offset and of width bitCount
val myBool = myBits(3, 2 bits)
Return the bit at index bitId
Return the bit at index bitId
val myBool = myBits(myUInt)
Return the bit at index bitId
Return the bit at index bitId
val myBool = myBits(3)
Cast data to Bits
Cast data to Bits
Create a data set to 0
Create a data set to 0
Resize the bitVector to width
Resize the bitVector to width
a resized bitVector
val res = myBits.resize(10)
Left rotation of that bits
Right rotation of that bits
Concatenation between two data
Concatenation between two data
BitVector is not equal to MaskedLiteral
Compare a BitVector with a MaskedLiteral (M"110--0")
Compare a BitVector with a MaskedLiteral (M"110--0")
the maskedLiteral
a Bool data containing the result of the comparison
val myBool = myBits === M"0-1"
Allow a Data of an io Bundle to be directionless
Allow a Data of an io Bundle to be directionless
See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Design%20errors/iobundle.html
Allow a Data to be overriden
Allow a Data to be overriden
See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Design%20errors/assignment_overlap.html
Allow a register to be partially assigned
Allow a register to be partially assigned
Allow a register to have only an init (no assignments)
Allow a register to have only an init (no assignments)
See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Design%20errors/unassigned_register.html#register-with-only-init
Logical AND of all bits
Return a range of bits
Return a range of bits
val myBool = myBits(3 downto 1)
Cast the BitVector into a Vector of Bool
Cast the BitVector into a Vector of Bool
a vector of Bool
set a data as inout
Set a data as input
Set a data as output
Clear all bits
Drop lowerst n bits
Drop lowerst n bits
data10bits(9 downto 4)
val res = data10bits.drop(4)
Drop highest n bits
Drop highest n bits
data10bits(5 downto 0)
val res = data10bits.dropHigh(4)
flip the direction of the data
flip the direction of the data
Return the width of the data
Get current component with all parents
Get current component with all parents
Return the width
Does the base type have initial value
Does the base type have initial value
Return the upper bound
Is the baseType a node
Is the baseType a node
Is the basetype using reset signal
Is the basetype using reset signal
Is the basetype using soft reset signal
Is the basetype using soft reset signal
Check if the baseType is vital
Check if the baseType is vital
Return the least significant bit
Return the most significant bit
Extract a range of bits of the BitVector
Extract a range of bits of the BitVector
Extract a bit of the BitVector
Extract a bit of the BitVector
Put the combinatorial logic driving this signal in a separate process
Put the combinatorial logic driving this signal in a separate process
Disable combinatorial loop checking for this Data
Disable combinatorial loop checking for this Data
See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Design%20errors/combinatorial_loop.html
Logical OR of all bits
Pull a signal to the top level (use for debugging)
Pull a signal to the top level (use for debugging)
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
Remove all assignments of the base type
Resized data regarding target
Resized data regarding target
root interface
root interface
Left rotation of that Bits
Right rotation of that Bits
Set all bits to value
Set all bits to value
Set baseType to Combinatorial
remove the direction (in,out,inout) to a data
Set baseType to reg
Set baseType to Node
Set baseType to Node
Set the baseType to vital
Set the baseType to vital
Recursively set baseType to reg only for output
Recursively set baseType to reg only for output
Set the width of the BitVector
Set the width of the BitVector
the width of the data
the BitVector of a given size
apart by a list of width
apart by a list of width
(List(A(1 downto 0), A(2 downto 4), A(9 downto 3))
val res = A.sliceBy(2, 3, 5) val res = A.sliceBy(List(2, 3, 5))
Split at n st bits
Split at n st bits
(data10bits(8 downto 4), data10bits(3 downto 0))
val res = data10bits.splitAt(4)
Split the BitVector into slice of x bits
Split the BitVector into slice of x bits
the width of the slice
allow subdivideIn to generate vectors with varying size
a Vector of slices
val res = myBits.subdivideIn(3 bits)
Split the BitVector into x slice
Split the BitVector into x slice
the width of the slice
allow subdivideIn to generate vectors with varying size
a Vector of slices
val res = myBits.subdivideIn(3 slices)
Take lowerst n bits
Take lowerst n bits
data10bits(3 downto 0)
val res = data10bits.take(4)
Take highest n bits
Take highest n bits
data10bits(9 downto 6)
val res = data10bits.takeHigh(4)
Logical XOR of all bits
(Since version ???) use setAsDirectionLess instead
(Since version ) see corresponding Javadoc for more information.
Generate this if condition is true
Generate this if condition is true
does not work with <>, use 'someBool generate Type()' or 'if(condition) Type() else null' instead
Return the range
Return the range
Use bitsRange instead
BitVector is a family of types for storing multiple bits of information in a single value. This type has three subtypes that can be used to model different behaviours:
BitVector Documentation