SpinalConfig

Instance Constructors

new SpinalConfig(mode: SpinalMode = null, flags: HashSet[Any] = mutable.HashSet[Any](), debugComponents: HashSet[Class[_]] = mutable.HashSet[Class[_]](), keepAll: Boolean = false, defaultConfigForClockDomains: ClockDomainConfig = ClockDomainConfig(), onlyStdLogicVectorAtTopLevelIo: Boolean = false, defaultClockDomainFrequency: IClockDomainFrequency = UnknownFrequency(), targetDirectory: String = SpinalConfig.defaultTargetDirectory, oneFilePerComponent: Boolean = false, netlistFileName: String = null, dumpWave: DumpWaveConfig = null, globalPrefix: String = "", privateNamespace: Boolean = false, formalAsserts: Boolean = false, anonymSignalPrefix: String = null, device: Device = Device(), inlineRom: Boolean = false, caseRom: Boolean = false, romReuse: Boolean = false, genVhdlPkg: Boolean = true, verbose: Boolean = false, mergeAsyncProcess: Boolean = false, mergeSyncProcess: Boolean = true, asyncResetCombSensitivity: Boolean = false, anonymSignalUniqueness: Boolean = false, inlineConditionalExpression: Boolean = false, nameWhenByFile: Boolean = true, genLineComments: Boolean = false, noRandBoot: Boolean = false, randBootFixValue: Boolean = true, noAssert: Boolean = false, fixToWithWrap: Boolean = true, headerWithDate: Boolean = false, headerWithRepoHash: Boolean = true, removePruned: Boolean = false, allowOutOfRangeLiterals: Boolean = false, dontCareGenAsZero: Boolean = false, obfuscateNames: Boolean = false, normalizeComponentClockDomainName: Boolean = false, devicePhaseHandler: PhaseDeviceHandler = PhaseDeviceDefault, phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) ⇒ Unit] = ..., transformationPhases: ArrayBuffer[Phase] = ArrayBuffer[Phase](), memBlackBoxers: ArrayBuffer[Phase] = ..., rtlHeader: String = null, scopeProperties: LinkedHashMap[ScopeProperty[_], Any] = ..., _withEnumString: Boolean = true, enumPrefixEnable: Boolean = true, enumGlobalEnable: Boolean = false, bitVectorWidthMax: Int = 4096, singleTopLevel: Boolean = true, noAssertAtTimeZero: Boolean = false, cutLongExpressions: Boolean = true, withTimescale: Boolean = true, printFilelist: Boolean = true, emitFullComponentBindings: Boolean = true, svInterface: Boolean = false)

Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def addOptions(parser: OptionParser[Unit]): Unit
def addStandardMemBlackboxing(policy: MemBlackboxingPolicy): SpinalConfig.this.type
def addTransformationPhase(phase: Phase): SpinalConfig
val allowOutOfRangeLiterals: Boolean
val anonymSignalPrefix: String
val anonymSignalUniqueness: Boolean
def apply[T <: Component](gen: ⇒ T): SpinalReport[T]
def applyToGlobalData(globalData: GlobalData): Unit
final def asInstanceOf[T0]: T0

Definition Classes
Any
val asyncResetCombSensitivity: Boolean
val bitVectorWidthMax: Int
val caseRom: Boolean
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@HotSpotIntrinsicCandidate() @throws( ... )
var cutLongExpressions: Boolean
val debugComponents: HashSet[Class[_]]
val defaultClockDomainFrequency: IClockDomainFrequency
val defaultConfigForClockDomains: ClockDomainConfig
val device: Device
var devicePhaseHandler: PhaseDeviceHandler
val dontCareGenAsZero: Boolean
def dumpWave(depth: Int = 0, vcdPath: String = "wave.vcd"): SpinalConfig
val dumpWave: DumpWaveConfig
var emitFullComponentBindings: Boolean
var enumGlobalEnable: Boolean
var enumPrefixEnable: Boolean
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
val fixToWithWrap: Boolean
val flags: HashSet[Any]
var formalAsserts: Boolean
var genLineComments: Boolean
val genVhdlPkg: Boolean
def generate[T <: Component](gen: ⇒ T): SpinalReport[T]
def generateSystemVerilog[T <: Component](gen: ⇒ T): SpinalReport[T]
def generateVerilog[T <: Component](gen: ⇒ T): SpinalReport[T]
def generateVhdl[T <: Component](gen: ⇒ T): SpinalReport[T]
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
Annotations
@HotSpotIntrinsicCandidate()
val globalPrefix: String
val headerWithDate: Boolean
val headerWithRepoHash: Boolean
def includeFormal: SpinalConfig.this.type
def includeSimulation: SpinalConfig.this.type
def includeSynthesis: SpinalConfig.this.type
val inlineConditionalExpression: Boolean
val inlineRom: Boolean
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
def isSystemVerilog: Boolean
val keepAll: Boolean
val memBlackBoxers: ArrayBuffer[Phase]
val mergeAsyncProcess: Boolean
val mergeSyncProcess: Boolean
val mode: SpinalMode
val nameWhenByFile: Boolean
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
var netlistFileName: String
val noAssert: Boolean
var noAssertAtTimeZero: Boolean
val noRandBoot: Boolean
var normalizeComponentClockDomainName: Boolean
final def notify(): Unit

Definition Classes
AnyRef
Annotations
@HotSpotIntrinsicCandidate()
final def notifyAll(): Unit

Definition Classes
AnyRef
Annotations
@HotSpotIntrinsicCandidate()
val obfuscateNames: Boolean
val oneFilePerComponent: Boolean
val onlyStdLogicVectorAtTopLevelIo: Boolean
val phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) ⇒ Unit]
var printFilelist: Boolean
var privateNamespace: Boolean
val randBootFixValue: Boolean
val removePruned: Boolean
val romReuse: Boolean
val rtlHeader: String
val scopeProperties: LinkedHashMap[ScopeProperty[_], Any]
def setScopeProperty[T](value: ScopePropertyValue): SpinalConfig.this.type
def setScopeProperty[T](scopeProperty: ScopeProperty[T], value: T): SpinalConfig.this.type
var singleTopLevel: Boolean
var svInterface: Boolean
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
var targetDirectory: String
val transformationPhases: ArrayBuffer[Phase]
val verbose: Boolean
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
def withGlobalEnum: SpinalConfig.this.type
def withLineComment: SpinalConfig.this.type
def withPrivateNamespace: SpinalConfig.this.type
var withTimescale: Boolean
def withoutAssert: SpinalConfig
def withoutEnumString(): SpinalConfig.this.type
def withoutLineComment: SpinalConfig.this.type

Deprecated Value Members

def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@Deprecated @deprecated @throws( classOf[java.lang.Throwable] )
Deprecated
(Since version ) see corresponding Javadoc for more information.

Related Docs: object SpinalConfig | package core

Instance Constructors

Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

def addOptions(parser: OptionParser[Unit]): Unit

def addStandardMemBlackboxing(policy: MemBlackboxingPolicy): SpinalConfig.this.type

def addTransformationPhase(phase: Phase): SpinalConfig

val allowOutOfRangeLiterals: Boolean

val anonymSignalPrefix: String

val anonymSignalUniqueness: Boolean

def apply[T <: Component](gen: ⇒ T): SpinalReport[T]

def applyToGlobalData(globalData: GlobalData): Unit

final def asInstanceOf[T0]: T0

val asyncResetCombSensitivity: Boolean

val bitVectorWidthMax: Int

val caseRom: Boolean

def clone(): AnyRef

var cutLongExpressions: Boolean

val debugComponents: HashSet[Class[_]]

val defaultClockDomainFrequency: IClockDomainFrequency

val defaultConfigForClockDomains: ClockDomainConfig

val device: Device

var devicePhaseHandler: PhaseDeviceHandler

val dontCareGenAsZero: Boolean

def dumpWave(depth: Int = 0, vcdPath: String = "wave.vcd"): SpinalConfig

val dumpWave: DumpWaveConfig

var emitFullComponentBindings: Boolean

var enumGlobalEnable: Boolean

var enumPrefixEnable: Boolean

final def eq(arg0: AnyRef): Boolean

val fixToWithWrap: Boolean

val flags: HashSet[Any]

var formalAsserts: Boolean

var genLineComments: Boolean

val genVhdlPkg: Boolean

def generate[T <: Component](gen: ⇒ T): SpinalReport[T]

def generateSystemVerilog[T <: Component](gen: ⇒ T): SpinalReport[T]

def generateVerilog[T <: Component](gen: ⇒ T): SpinalReport[T]

def generateVhdl[T <: Component](gen: ⇒ T): SpinalReport[T]

final def getClass(): Class[_]

val globalPrefix: String

val headerWithDate: Boolean

val headerWithRepoHash: Boolean

def includeFormal: SpinalConfig.this.type

def includeSimulation: SpinalConfig.this.type

def includeSynthesis: SpinalConfig.this.type

val inlineConditionalExpression: Boolean

val inlineRom: Boolean

final def isInstanceOf[T0]: Boolean

def isSystemVerilog: Boolean

val keepAll: Boolean

val memBlackBoxers: ArrayBuffer[Phase]

val mergeAsyncProcess: Boolean

val mergeSyncProcess: Boolean

val mode: SpinalMode

val nameWhenByFile: Boolean

final def ne(arg0: AnyRef): Boolean

var netlistFileName: String

val noAssert: Boolean

var noAssertAtTimeZero: Boolean

val noRandBoot: Boolean

var normalizeComponentClockDomainName: Boolean

final def notify(): Unit

final def notifyAll(): Unit

val obfuscateNames: Boolean

val oneFilePerComponent: Boolean

val onlyStdLogicVectorAtTopLevelIo: Boolean

val phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) ⇒ Unit]

var printFilelist: Boolean

var privateNamespace: Boolean

val randBootFixValue: Boolean

val removePruned: Boolean

val romReuse: Boolean

val rtlHeader: String

val scopeProperties: LinkedHashMap[ScopeProperty[_], Any]

def setScopeProperty[T](value: ScopePropertyValue): SpinalConfig.this.type

def setScopeProperty[T](scopeProperty: ScopeProperty[T], value: T): SpinalConfig.this.type