SpinalStruct
Related Doc:
package core
Concatenation between two data
Concatenation between two data
Assign a data to this
Assign a data to this
Auto connection between two data
Auto connection between two data
Comparison between two data
Comparison between two data
Use as \= to have the same behavioral as VHDL variable
Use as \= to have the same behavioral as VHDL variable
Allow a Data of an io Bundle to be directionless
Allow a Data of an io Bundle to be directionless
See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Design%20errors/iobundle.html
Allow a Data to be overriden
Allow a Data to be overriden
See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Design%20errors/assignment_overlap.html
Allow a register to be partially assigned
Allow a register to be partially assigned
Allow a register to have only an init (no assignments)
Allow a register to have only an init (no assignments)
See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Design%20errors/unassigned_register.html#register-with-only-init
Cast data to Bits
Cast data to Bits
set a data as inout
set a data as inout
Set a data as input
Set a data as input
Set a data as output
Set a data as output
Assign the bundle with an other bundle by name
Assign all possible signal fo the bundle with an other bundle by name
Set a default value to a data
Set a default value to a data
flip the direction of the data
flip the direction of the data
For a register, get the value it will have at the next clock, as a combinational signal.
Return the width of the data
Return the width of the data
Get current component with all parents
Get current component with all parents
Create a data set to 0
Create a data set to 0
Does the base type have initial value
Does the base type have initial value
Set initial value to a data
Set initial value to a data
Is the baseType a node
Is the baseType a node
Is the basetype using reset signal
Is the basetype using reset signal
Is the basetype using soft reset signal
Is the basetype using soft reset signal
Check if the baseType is vital
Check if the baseType is vital
Put the combinatorial logic driving this signal in a separate process
Put the combinatorial logic driving this signal in a separate process
Disable combinatorial loop checking for this Data
Disable combinatorial loop checking for this Data
See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Design%20errors/combinatorial_loop.html
Pull a signal to the top level (use for debugging)
Pull a signal to the top level (use for debugging)
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
Remove all assignments of the base type
Resized data regarding target
Resized data regarding target
root interface
root interface
Set baseType to Combinatorial
Set baseType to Combinatorial
remove the direction (in,out,inout) to a data
remove the direction (in,out,inout) to a data
Set baseType to reg
Set baseType to reg
Set baseType to Node
Set baseType to Node
Set the baseType to vital
Set the baseType to vital
Recursively set baseType to reg only for output
Recursively set baseType to reg only for output
Underlying structure name to use if not the subclass name.
(Since version ???) use setAsDirectionLess instead
(Since version ) see corresponding Javadoc for more information.
Generate this if condition is true
Generate this if condition is true
does not work with <>, use 'someBool generate Type()' or 'if(condition) Type() else null' instead
Class representing Verilog Struct and VHDL Record data types.