Vec
Related Doc:
package core
Concatenation between two data
Concatenation between two data
Allow a Data of an io Bundle to be directionless
Allow a Data of an io Bundle to be directionless
See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Design%20errors/iobundle.html
Allow a Data to be overriden
Allow a Data to be overriden
See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Design%20errors/assignment_overlap.html
Allow a register to be partially assigned
Allow a register to be partially assigned
Allow a register to have only an init (no assignments)
Allow a register to have only an init (no assignments)
See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Design%20errors/unassigned_register.html#register-with-only-init
Access an element of the vector by an UInt index
Access an element of the vector by an Int index
Access an element of the vector by an Int index
Cast data to Bits
set a data as inout
Set a data as input
Set a data as output
flip the direction of the data
For a register, get the value it will have at the next clock, as a combinational signal.
For a register, get the value it will have at the next clock, as a combinational signal.
Return the width of the data
Get current component with all parents
Get current component with all parents
Create a data set to 0
Put the combinatorial logic driving this signal in a separate process
Put the combinatorial logic driving this signal in a separate process
Disable combinatorial loop checking for this Data
Disable combinatorial loop checking for this Data
See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Design%20errors/combinatorial_loop.html
Access an element of the vector by a oneHot value
Pull a signal to the top level (use for debugging)
Pull a signal to the top level (use for debugging)
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
Resized data regarding target
Resized data regarding target
root interface
root interface
(Changed in version 2.9.0) The behavior of scanRight has changed. The previous behavior can be reproduced with scanRight.reverse.
Set baseType to Combinatorial
remove the direction (in,out,inout) to a data
Set baseType to reg
Recursively set baseType to reg only for output
Recursively set baseType to reg only for output
(Changed in version 2.9.0) transpose throws an IllegalArgumentException if collections are not uniformly sized.
(Since version ???) use setAsDirectionLess instead
(Since version ) see corresponding Javadoc for more information.
Generate this if condition is true
Generate this if condition is true
does not work with <>, use 'someBool generate Type()' or 'if(condition) Type() else null' instead
The Vec is a composite type that defines a group of indexed signals (of any SpinalHDL basic type) under a single name
Vec Documentation