Interface

final def !=(arg0: Any): Boolean

def ##(right: Data): Bits

Concatenation between two signals

final def ##(): Int

def #*(count: Int): Bits

final def ==(arg0: Any): Boolean

val IFGeneric: LinkedHashMap[(Data, String), String]

def IFparent: Data

var _spinalTags: LinkedHashSet[SpinalTag]

def addAttribute(attribute: Attribute): Interface.this.type

def addAttribute(name: String, value: Int): Interface.this.type

def addAttribute(name: String, value: String): Interface.this.type

def addAttribute(name: String): Interface.this.type

def addGeneric(name: String, that: Any, default: String = null): String

def addParameter(name: String, that: Any, default: String = null): String

def addTag[T <: SpinalTag](spinalTag: T): Interface.this.type

def addTags(h: SpinalTag, tail: SpinalTag*): Interface.this.type

def addTags[T <: SpinalTag](tags: Iterable[T]): Interface.this.type

def allModPort: List[String]

def allowDirectionLessIo(): Interface.this.type

Allow a signal of an io Bundle to be directionless.

def allowOverride(): Interface.this.type

Allow a signal to be overridden.

def allowPartialyAssigned(): Interface.this.type

Allow a register to be partially assigned

def allowPruning(): Interface.this.type

def allowSimplifyIt(): Interface.this.type

def allowUnsetRegToAvoidLatch(): Interface.this.type

Allow a register to have only an init (no assignments)

def as[T <: Data](dataType: HardType[T]): T

def asBits: Bits

Cast signal to Bits

def asData: Data

def asInOut(): Interface.this.type

Set a signal as inout

def asInput(): Interface.this.type

Set a data as input

final def asInstanceOf[T0]: T0

def asOutput(): Interface.this.type

Set a data as output

def assignAllByName(that: Bundle): Unit

Assign the bundle with an other bundle by name

def assignDontCare(): Interface.this.type

def assignDontCareToUnasigned(): Interface.this.type

def assignFormalRandom(kind: RandomExpKind): Unit

final def assignFrom(that: AnyRef, target: AnyRef = this)(implicit loc: Location): Unit

def assignFromBits(bits: Bits, hi: Int, lo: Int): Unit

def assignFromBits(bits: Bits): Unit

def assignFromBits(bits: Bits, offset: Int, bitCount: BitCount): Unit

def assignFromImpl(that: AnyRef, target: AnyRef, kind: AnyRef)(implicit loc: Location): Unit

def assignSomeByName(that: Bundle): Unit

Assign all possible signal fo the bundle with an other bundle by name

def assignUnassignedByName(that: MultiData): Unit

def bundleAssign(that: Bundle)(f: (Data, Data) ⇒ Unit): Unit

def callModPort(s: String): Unit

def checkDir(that: Bundle): Boolean

for interface find modport

def checkModport(): List[String]

def clearAll(): Interface.this.type

def clone(): Interface

def component: Component

final def compositAssignFrom(that: AnyRef, target: AnyRef, kind: AnyRef)(implicit loc: Location): Unit

var compositeAssign: Assignable

def copyDirectionOfImpl(that: Data): Interface.this.type

var definitionName: String

def dirString(): String

def dontSimplifyIt(): Interface.this.type

def elements: ArrayBuffer[(String, Data)]

var elementsCache: ArrayBuffer[(String, Data)]

def elementsString: String

final def eq(arg0: AnyRef): Boolean

def equals(obj: Any): Boolean

def existsTag(cond: (SpinalTag) ⇒ Boolean): Boolean

def filterTag(cond: (SpinalTag) ⇒ Boolean): Iterable[SpinalTag]

def find(name: String): Data

def findTag(cond: (SpinalTag) ⇒ Boolean): Option[SpinalTag]

def flatten: Seq[BaseType]

def flattenForeach(body: (BaseType) ⇒ Unit): Unit

def flattenLocalName: Seq[String]

def flip(): Interface.this.type

Flip the direction of the signal.

def foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit

def foreachTag(body: (SpinalTag) ⇒ Unit): Unit

def freeze(): Interface.this.type

val genericElements: ArrayBuffer[(String, Any, String)]

def getAheadValue(): Interface.this.type

For a register, get the value it will have at the next clock, as a combinational signal.

def getBitsWidth: Int

Return the width of the data

final def getClass(): Class[_]

def getComponent(): Component

def getComponents(): Seq[Component]

Get current component with all parents

def getDirection: IODirection

def getDisplayName(): String

def getInstanceCounter: Int

def getMode: Byte

def getMuxType[T <: Data](list: TraversableOnce[T]): HardType[T]

def getName(default: String): String

def getName(): String

def getPartialName(): String

def getPath(from: Component, to: Component): Seq[Component]

def getRealSource: Any

def getRealSourceNoRec: Any

def getRefOwnersChain(): List[Any]

def getRootParent: Data

def getRtlPath(separator: String = "/"): String

def getScalaLocationLong: String

def getScalaLocationShort: String

def getScalaTrace(): Throwable

def getTag[T <: SpinalTag](clazz: Class[T]): Option[T]

def getTags(): LinkedHashSet[SpinalTag]

def getTypeString: String

def getZero: Interface.this.type

Create a signal set to 0

var globalData: GlobalData

var hardtype: HardType[_]

def hasTag[T <: SpinalTag](clazz: Class[T]): Boolean

def hasTag(spinalTag: SpinalTag): Boolean

def hashCode(): Int

final def initFrom(that: AnyRef, target: AnyRef = this): Unit

def instanceAttributes(language: Language): Iterable[Attribute]

def instanceAttributes: Iterable[Attribute]

def isAnalog: Boolean

def isComb: Boolean

def isCompletelyUnnamed: Boolean

def isDirectionLess: Boolean

def isEmptyOfTag: Boolean

def isInOut: Boolean

def isInput: Boolean

def isInputOrInOut: Boolean

final def isInstanceOf[T0]: Boolean

final def isNamed: Boolean

def isOutput: Boolean

def isOutputOrInOut: Boolean

def isPriorityApplicable(namePriority: Byte): Boolean

def isReg: Boolean

def isRegOnAssign: Boolean

def isUnnamed: Boolean

var name: String

var nameableRef: Nameable

final def ne(arg0: AnyRef): Boolean

def noBackendCombMerge(): Interface.this.type

Put the combinatorial logic driving this signal in a separate process

def noCombLoopCheck(): Interface.this.type

Disable combinatorial loop checking for this Data

def notSVIF(): Unit

def notSVIFthisLevel(): Unit

final def notify(): Unit

final def notifyAll(): Unit

def onEachAttributes(doIt: (Attribute) ⇒ Unit): Unit

def overrideLocalName(name: String): Interface.this.type

var parent: Data

var parentScope: ScopeStatement

def pull(propagateName: Boolean): Interface.this.type

def pull(): Interface.this.type

Pull a signal to the top level (use for debugging)

def purify(): Interface.this.type

def randBoot(u: Unit): Interface.this.type

Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)

var refOwner: RefOwnerType

def reflectNames(): Unit

def removeAssignments(data: Boolean = true, init: Boolean = true, initial: Boolean = true): Interface.this.type

def removeDataAssignments(): Interface.this.type

def removeInitAssignments(): Interface.this.type

def removeTag(spinalTag: SpinalTag): Interface.this.type

def removeTags(tags: Iterable[SpinalTag]): Interface.this.type

def resized: Interface.this.type

Return a version of the signal which is allowed to be automatically resized where needed.

def rootIF(): Interface

root interface

def rootIFList(): List[Interface]

def rootIFrec(now: Data, lastRoot: List[Interface]): List[Interface]

var scalaTrace: Throwable

def setAll(): Interface.this.type

def setAsAnalog(): Interface.this.type

def setAsComb(): Interface.this.type

Set baseType to Combinatorial

def setAsDirectionLess(): Interface.this.type

Remove the direction (in, out, inout) to a signal

def setAsReg(): Interface.this.type

Set baseType to reg

def setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): Interface.this.type

def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): Interface.this.type

def setCompositeName(nameable: Nameable, postfix: String): Interface.this.type

def setCompositeName(nameable: Nameable, namePriority: Byte): Interface.this.type

def setCompositeName(nameable: Nameable, weak: Boolean): Interface.this.type

def setCompositeName(nameable: Nameable): Interface.this.type

def setDefinitionName(name: String): Interface.this.type

Set the definition name of the component

def setLambdaName(isNameBody: ⇒ Boolean)(nameGen: ⇒ String): Interface.this.type

def setName(name: String, namePriority: Byte): Interface.this.type

def setName(name: String, weak: Boolean): Interface.this.type

def setName(name: String): Interface.this.type

def setNameAsWeak(): Interface.this.type

def setOutputAsReg(): Interface.this.type

Recursively set baseType to reg only for output

def setPartialName(name: String, namePriority: Byte, owner: Any): Interface.this.type

def setPartialName(name: String, namePriority: Byte): Interface.this.type

def setPartialName(name: String, weak: Boolean): Interface.this.type

def setPartialName(owner: Nameable, name: String, namePriority: Byte): Interface.this.type

def setPartialName(owner: Nameable, name: String, weak: Boolean): Interface.this.type

def setPartialName(name: String): Interface.this.type

def setPartialName(owner: Nameable, name: String): Interface.this.type

def setPartialName(owner: Nameable): Interface.this.type

def setRefOwner(that: Any): Unit

def setScalaLocated(source: ScalaLocated): Interface.this.type

def setWeakName(name: String): Interface.this.type

def spinalTags: LinkedHashSet[SpinalTag]

final def synchronized[T0](arg0: ⇒ T0): T0

var thisIsNotSVIF: Boolean

def tieGeneric[T <: BitVector](signal: T, generic: String): LinkedHashMap[BitVector, String]

def tieIFParameter[T <: Interface](signal: T, signalParam: String, inputParam: String): LinkedHashMap[(Data, String), String]

def tieParameter[T <: BitVector](signal: T, parameter: String): LinkedHashMap[BitVector, String]

def toIo(): Interface.this.type

def toMuxInput[T <: Data](muxOutput: T): T

def toString(): String

def unfreeze(): Interface.this.type

def unsetName(): Interface.this.type

def valCallback[T](ref: T, name: String): T

def valCallbackOn(ref: Any, name: String, refs: Set[Any]): Unit

def valCallbackRec(ref: Any, name: String): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

final def wait(): Unit

val widthGeneric: LinkedHashMap[BitVector, String]

def wrapNext(): Interface.this.type

def zipByName(that: MultiData, rec: ArrayBuffer[(BaseType, BaseType)] = ArrayBuffer()): ArrayBuffer[(BaseType, BaseType)]

def asDirectionLess(): Interface.this.type

def finalize(): Unit

def genIf(cond: Boolean): Interface.this.type

Generate this if condition is true