Class/Object

spinal.core

SpinalConfig

Related Docs: object SpinalConfig | package core

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case class SpinalConfig(mode: SpinalMode = null, flags: HashSet[Any] = mutable.HashSet[Any](), debugComponents: HashSet[Class[_]] = mutable.HashSet[Class[_]](), keepAll: Boolean = false, defaultConfigForClockDomains: ClockDomainConfig = ClockDomainConfig(), onlyStdLogicVectorAtTopLevelIo: Boolean = false, defaultClockDomainFrequency: IClockDomainFrequency = UnknownFrequency(), targetDirectory: String = ".", oneFilePerComponent: Boolean = false, netlistFileName: String = null, dumpWave: DumpWaveConfig = null, globalPrefix: String = "", formalAsserts: Boolean = false, anonymSignalPrefix: String = null, device: Device = Device(), inlineRom: Boolean = false, genVhdlPkg: Boolean = true, verbose: Boolean = false, mergeAsyncProcess: Boolean = true, asyncResetCombSensitivity: Boolean = false, anonymSignalUniqueness: Boolean = false, noRandBoot: Boolean = false, noAssert: Boolean = false, phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) ⇒ Unit] = ..., transformationPhases: ArrayBuffer[Phase] = ArrayBuffer[Phase](), memBlackBoxers: ArrayBuffer[Phase] = ..., rtlHeader: String = null) extends Product with Serializable

Spinal configuration for the generation of the RTL

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Serializable, Serializable, Product, Equals, AnyRef, Any
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  1. SpinalConfig
  2. Serializable
  3. Serializable
  4. Product
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Instance Constructors

  1. new SpinalConfig(mode: SpinalMode = null, flags: HashSet[Any] = mutable.HashSet[Any](), debugComponents: HashSet[Class[_]] = mutable.HashSet[Class[_]](), keepAll: Boolean = false, defaultConfigForClockDomains: ClockDomainConfig = ClockDomainConfig(), onlyStdLogicVectorAtTopLevelIo: Boolean = false, defaultClockDomainFrequency: IClockDomainFrequency = UnknownFrequency(), targetDirectory: String = ".", oneFilePerComponent: Boolean = false, netlistFileName: String = null, dumpWave: DumpWaveConfig = null, globalPrefix: String = "", formalAsserts: Boolean = false, anonymSignalPrefix: String = null, device: Device = Device(), inlineRom: Boolean = false, genVhdlPkg: Boolean = true, verbose: Boolean = false, mergeAsyncProcess: Boolean = true, asyncResetCombSensitivity: Boolean = false, anonymSignalUniqueness: Boolean = false, noRandBoot: Boolean = false, noAssert: Boolean = false, phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) ⇒ Unit] = ..., transformationPhases: ArrayBuffer[Phase] = ArrayBuffer[Phase](), memBlackBoxers: ArrayBuffer[Phase] = ..., rtlHeader: String = null)

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Value Members

  1. final def !=(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any

  2. final def ##(): Int

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    Definition Classes
    AnyRef → Any

  3. final def ==(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any

  4. def addStandardMemBlackboxing(policy: MemBlackboxingPolicy): SpinalConfig.this.type

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  5. def addTransformationPhase(phase: Phase): SpinalConfig

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  6. val anonymSignalPrefix: String

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  7. val anonymSignalUniqueness: Boolean

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  8. def apply[T <: Component](gen: ⇒ T): SpinalReport[T]

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  9. def applyToGlobalData(globalData: GlobalData): Unit

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  10. final def asInstanceOf[T0]: T0

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    Definition Classes
    Any

  11. val asyncResetCombSensitivity: Boolean

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  12. def clone(): AnyRef

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  13. val debugComponents: HashSet[Class[_]]

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  14. val defaultClockDomainFrequency: IClockDomainFrequency

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  15. val defaultConfigForClockDomains: ClockDomainConfig

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  16. val device: Device

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  17. def dumpWave(depth: Int = 0, vcdPath: String = "wave.vcd"): SpinalConfig

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  18. val dumpWave: DumpWaveConfig

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  19. final def eq(arg0: AnyRef): Boolean

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    Definition Classes
    AnyRef

  20. def finalize(): Unit

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )

  21. val flags: HashSet[Any]

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  22. var formalAsserts: Boolean

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  23. val genVhdlPkg: Boolean

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  24. def generate[T <: Component](gen: ⇒ T): SpinalReport[T]

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  25. def generateSystemVerilog[T <: Component](gen: ⇒ T): SpinalReport[T]

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  26. def generateVerilog[T <: Component](gen: ⇒ T): SpinalReport[T]

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  27. def generateVhdl[T <: Component](gen: ⇒ T): SpinalReport[T]

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  28. final def getClass(): Class[_]

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    Definition Classes
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  29. val globalPrefix: String

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  30. def includeFormal: SpinalConfig.this.type

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  31. def includeSimulation: SpinalConfig.this.type

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  32. def includeSynthesis: SpinalConfig.this.type

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  33. val inlineRom: Boolean

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  34. final def isInstanceOf[T0]: Boolean

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    Definition Classes
    Any

  35. def isSystemVerilog: Boolean

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  36. val keepAll: Boolean

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  37. val memBlackBoxers: ArrayBuffer[Phase]

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  38. val mergeAsyncProcess: Boolean

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  39. val mode: SpinalMode

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  40. final def ne(arg0: AnyRef): Boolean

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    Definition Classes
    AnyRef

  41. val netlistFileName: String

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  42. val noAssert: Boolean

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  43. val noRandBoot: Boolean

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  44. final def notify(): Unit

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    Definition Classes
    AnyRef

  45. final def notifyAll(): Unit

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    Definition Classes
    AnyRef

  46. val oneFilePerComponent: Boolean

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  47. val onlyStdLogicVectorAtTopLevelIo: Boolean

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  48. val phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) ⇒ Unit]

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  49. val rtlHeader: String

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  50. final def synchronized[T0](arg0: ⇒ T0): T0

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    Definition Classes
    AnyRef

  51. val targetDirectory: String

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  52. val transformationPhases: ArrayBuffer[Phase]

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  53. val verbose: Boolean

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  54. final def wait(): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  55. final def wait(arg0: Long, arg1: Int): Unit

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    Definition Classes
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    Annotations
    @throws( ... )

  56. final def wait(arg0: Long): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  57. def withoutAssert: SpinalConfig

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Inherited from Serializable

Inherited from Serializable

Inherited from Product

Inherited from Equals

Inherited from AnyRef

Inherited from Any

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