UInt

final def !=(arg0: Any): Boolean

def ##(right: Data): Bits

Concatenation between two data

final def ##(): Int

def %(right: UInt): UInt

Modulo

def &(right: UInt): UInt

Logical AND operator

def *(right: UInt): UInt

Multiplication

def +(right: UInt): UInt

Addition

def -(right: UInt): UInt

Substraction

def /(right: UInt): UInt

Division

def :=(rangesValue: (Any, Any), _rangesValues: (Any, Any)*): Unit

Assign a range value to an UInt

def :=(that: UInt): Unit

Assign a data to this

def <(right: UInt): Bool

Is less than right

def <<(that: UInt): UInt

Logical shift Left (output width will increase of w(this) + max(that) bits

def <<(that: Int): UInt

Logical left shift (w(T) = w(this) + shift)

def <=(right: UInt): Bool

Is equal or less than right

def <>(that: UInt): Unit

Auto connection between two data

def =/=(that: UInt): Bool

def =/=(that: MaskedLiteral): Bool

BitVector is not equal to MaskedLiteral

final def ==(arg0: Any): Boolean

def ===(that: UInt): Bool

Comparison between two data

def ===(that: MaskedLiteral): Bool

Compare a BitVector with a MaskedLiteral (M"110--0")

def >(right: UInt): Bool

Is greater than right

def >=(right: UInt): Bool

Is equal or greater than right

def >>(that: UInt): UInt

Logical shift Right (output width = input width)

def >>(that: Int): UInt

Logical right shift (w(T) = w(this) - shift)

def @@(that: Bool): UInt

Concatenation between a UInt and a Bool

def @@(that: UInt): UInt

Concatenation between two UInt

def \(that: UInt): UInt

Use as \= to have the same behavioral thant VHDL variable

def ^(right: UInt): UInt

Logical XOR operator

def _data: UInt

var _spinalTags: Set[SpinalTag]

def addAttribute(attribute: Attribute): UInt.this.type

def addAttribute(name: String, value: String): UInt.this.type

def addAttribute(name: String): UInt.this.type

def addTag[T <: SpinalTag](spinalTag: T): UInt.this.type

def addTags[T <: SpinalTag](tags: Iterable[T]): UInt.this.type

var algoIncrementale: Int

var algoInt: Int

def allowDirectionLessIo: UInt.this.type

def allowOverride: UInt.this.type

Allow a data to be overrided

def allowPruning(): UInt.this.type

def allowSimplifyIt(): UInt.this.type

def allowUnsetRegToAvoidLatch: UInt.this.type

def andR: Bool

Logical AND of all bits

def apply(offset: UInt, bitCount: BitCount): UInt.this.type

Return a range of bits at offset and of width bitCount

def apply(offset: Int, bitCount: BitCount): UInt.this.type

Return a range of bits at offset and of width bitCount

def apply(bitId: UInt): Bool

Return the bit at index bitId

def apply(bitId: Int): Bool

Return the bit at index bitId

def apply(range: Range): UInt.this.type

Return a range of bits

def asBits: Bits

Cast data to Bits

def asBool: Bool

def asBools: Vec[Bool]

Cast the BitVector into a Vector of Bool

def asData: Data

def asInOut(): UInt.this.type

set a data as inout

def asInput(): UInt.this.type

Set a data as input

final def asInstanceOf[T0]: T0

def asOutput(): UInt.this.type

Set a data as output

def asSInt: SInt

Cast an UInt to a SInt

def assignDontCare(): UInt.this.type

final def assignFrom(that: AnyRef, target: AnyRef = this): Unit

def assignFromBits(bits: Bits, hi: Int, lo: Int): Unit

def assignFromBits(bits: Bits): Unit

def assignFromBits(bits: Bits, offset: Int, bitCount: BitCount): Unit

def assignMask(maskedLiteral: MaskedLiteral): Unit

Assign a mask to the output signal

def clearAll(): UInt.this.type

Clear all bits

var clockDomain: ClockDomain

def clone(): UInt.this.type

def component: Component

final def compositAssignFrom(that: AnyRef, target: AnyRef, kind: AnyRef): Unit

var compositeAssign: Assignable

def default(that: ⇒ UInt): UInt

Set a default value to a data

def dirString(): String

def dlcAppend(that: AssignmentStatement): UInt.this.type

def dlcForeach[T >: AssignmentStatement](func: (T) ⇒ Unit): Unit

def dlcHasOnlyOne: Boolean

var dlcHead: AssignmentStatement

def dlcIsEmpty: Boolean

var dlcLast: AssignmentStatement

def dlcPrepend(that: AssignmentStatement): UInt.this.type

def dontSimplifyIt(): UInt.this.type

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

def existsTag(cond: (SpinalTag) ⇒ Boolean): Boolean

def filterTag(cond: (SpinalTag) ⇒ Boolean): Iterable[SpinalTag]

def finalize(): Unit

def findTag(cond: (SpinalTag) ⇒ Boolean): Option[SpinalTag]

def flatten: Seq[BaseType]

def flattenForeach(body: (BaseType) ⇒ Unit): Unit

def flattenLocalName: Seq[String]

def flip(): UInt.this.type

flip the direction of the data

def foreachClockDomain(func: (ClockDomain) ⇒ Unit): Unit

def foreachDrivingExpression(func: (Expression) ⇒ Unit): Unit

def foreachExpression(func: (Expression) ⇒ Unit): Unit

def foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit

def foreachStatements(func: (AssignmentStatement) ⇒ Unit): Unit

def genIf(cond: Boolean): UInt.this.type

Generate this if condition is true

def getAllTrue: UInt.this.type

def getBitsWidth: Int

Return the width of the data

final def getClass(): Class[_]

def getComponent(): Component

def getComponents(): Seq[Component]

Get current component with all parents

def getDisplayName(): String

def getDrivingReg: UInt.this.type

def getInstanceCounter: Int

def getMode: Byte

def getName(default: String): String

def getName(): String

def getRealSource: Any

def getRealSourceNoRec: Any

def getRefOwnersChain(): List[Any]

def getRootParent: Data

def getScalaLocationLong: String

def getScalaLocationShort: String

def getScalaTrace(): Throwable

def getSingleDriver: Option[UInt.this.type]

def getTag[T <: SpinalTag](clazz: Class[T]): Option[T]

def getTags(): Set[SpinalTag]

def getTypeObject: TypeUInt.type

def getWidth: Int

def getWidthNoInferation: Int

Return the width

def getWidthStringNoInferation: String

def getZero: UInt.this.type

Create a data set to 0

def getZeroUnconstrained: UInt.this.type

val globalData: GlobalData

def hasAssignement: Boolean

def hasInit: Boolean

Does the base type have initial value

def hasOnlyOneStatement: Boolean

def hasTag[T <: SpinalTag](clazz: Class[T]): Boolean

def hasTag(spinalTag: SpinalTag): Boolean

def hashCode(): Int

def head: AssignmentStatement

def high: Int

Return the upper bound

def init(that: UInt): UInt

Set inital value to a data

final def initFrom(that: AnyRef, target: AnyRef = this): Unit

def insertNext(s: Statement): Unit

def instanceAttributes(language: Language): Iterable[Attribute]

def instanceAttributes: Iterable[Attribute]

def isAnalog: Boolean

def isComb: Boolean

def isDirectionLess: Boolean

def isEmptyOfTag: Boolean

def isInOut: Boolean

def isInput: Boolean

def isInputOrInOut: Boolean

final def isInstanceOf[T0]: Boolean

def isNamed: Boolean

def isOutput: Boolean

def isOutputOrInOut: Boolean

def isPriorityApplicable(namePriority: Byte): Boolean

def isReg: Boolean

def isTypeNode: Boolean

Is the baseType a node

def isUnnamed: Boolean

def isUsingResetSignal: Boolean

Is the basetype using reset signal

def isUsingSoftResetSignal: Boolean

Is the basetype using soft reset signal

def isVital: Boolean

Check if the baseType is vital

def keep(): UInt.this.type

var lastScopeStatement: Statement

def lsb: Bool

Return the least significant bit

def max(right: UInt): UInt

Return the maximum value between this and right

def maxValue: BigInt

def min(right: UInt): UInt

Return the minimum value between this and right

def minValue: BigInt

def msb: Bool

Return the most significant bit

def mux[T2 <: Data](mappings: (Any, T2)*): T2

def muxList[T2 <: Data](defaultValue: T2, mappings: Seq[(Any, T2)]): T2

def muxList[T2 <: Data](mappings: Seq[(Any, T2)]): T2

def muxListDc[T2 <: Data](mappings: Seq[(Any, T2)]): T2

var name: String

var nameableRef: Nameable

final def ne(arg0: AnyRef): Boolean

def newExtract(offset: UInt, size: Int, extract: BitVectorRangedAccessFloating): UInt.this.type

Extract a range of bits of the BitVector

def newExtract(hi: Int, lo: Int, accessFactory: ⇒ BitVectorRangedAccessFixed): UInt.this.type

Extract a range of bits of the BitVector

def newExtract(bitId: UInt, extract: BitVectorBitAccessFloating): Bool

Extract a bit of the BitVector

def newExtract(bitId: Int, extract: BitVectorBitAccessFixed): Bool

Extract a bit of the BitVector

var nextScopeStatement: Statement

def noBackendCombMerge: UInt.this.type

def noCombLoopCheck: UInt.this.type

def normalizeInputs: Unit

final def notify(): Unit

final def notifyAll(): Unit

def onEachAttributes(doIt: (Attribute) ⇒ Unit): Unit

def opName: String

def orR: Bool

Logical OR of all bits

var parent: Data

var parentScope: ScopeStatement

def pull(): UInt.this.type

Pull a signal to the top level (use for debugging)

def purify(): UInt.this.type

def randBoot(): UInt.this.type

Usefull for register that doesn't need a reset value in RTL, but need a randome value for simulation (avoid x-propagation)

def range: Range

Return the range

var refOwner: RefOwnerType

def remapDrivingExpressions(func: (Expression) ⇒ Expression): Unit

def remapExpressions(func: (Expression) ⇒ Expression): Unit

def removeAssignments(): UInt.this.type

Remove all assignements of the base type

def removeStatement(): Unit

def removeStatementFromScope(): Unit

def removeTag(spinalTag: SpinalTag): UInt.this.type

def removeTags(tags: Iterable[SpinalTag]): UInt.this.type

def resize(width: BitCount): UInt

def resize(width: Int): UInt.this.type

Resize the bitVector to width

def resized: UInt.this.type

Resized data regarding target

def rootScopeStatement: ScopeStatement

def rotateLeft(that: Int): UInt

Left rotation of that bits

def rotateLeft(that: UInt): T

Left rotation of that Bits

def rotateRight(that: Int): UInt

Right rotation of that bits

def rotateRight(that: UInt): T

Right rotation of that Bits

def setAll(): UInt.this.type

Set all bits

def setAllTo(value: Bool): UInt.this.type

Set all bits to value

def setAllTo(value: Boolean): UInt.this.type

Set all bits to value

def setAsAnalog(): UInt.this.type

def setAsComb(): UInt.this.type

Set baseType to Combinatorial

def setAsDirectionLess(): UInt.this.type

remove the direction (in,out,inout) to a data

def setAsReg(): UInt.this.type

Set baseType to reg

def setAsTypeNode(): UInt.this.type

Set baseType to Node

def setAsVital(): UInt.this.type

Set the baseType to vital

def setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): UInt.this.type

def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): UInt.this.type

def setCompositeName(nameable: Nameable, postfix: String): UInt.this.type

def setCompositeName(nameable: Nameable, namePriority: Byte): UInt.this.type

def setCompositeName(nameable: Nameable, weak: Boolean): UInt.this.type

def setCompositeName(nameable: Nameable): UInt.this.type

def setName(name: String, namePriority: Byte): UInt.this.type

def setName(name: String, weak: Boolean): UInt.this.type

def setName(name: String): UInt.this.type

def setPartialName(name: String, namePriority: Byte): UInt.this.type

def setPartialName(name: String, weak: Boolean): UInt.this.type

def setPartialName(owner: Nameable, name: String, namePriority: Byte): UInt.this.type

def setPartialName(owner: Nameable, name: String, weak: Boolean): UInt.this.type

def setPartialName(name: String): UInt.this.type

def setPartialName(owner: Nameable, name: String): UInt.this.type

def setRefOwner(that: Any): Unit

def setScalaLocated(source: ScalaLocated): UInt.this.type

def setWeakName(name: String): UInt.this.type

def setWidth(width: Int): UInt.this.type

Set the width of the BitVector

def simplifyNode: Expression

def spinalTags: Set[SpinalTag]

def subdivideIn(sliceWidth: BitCount): Vec[T]

Split the BitVector into slice of x bits * @example

val res = myBits.subdiviedIn(3 bits)

def subdivideIn(sliceCount: SlicesCount): Vec[T]

Split the BitVector into x slice

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

def toStringMultiLine(): String

def twoComplement(enable: Bool): SInt

2'Complement

def unary_~: UInt

Inverse bitwise operator

def unsetName(): UInt.this.type

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

def walkDrivingExpressions(func: (Expression) ⇒ Unit): Unit

def walkExpression(func: (Expression) ⇒ Unit): Unit

def walkParentTreeStatements(func: (TreeStatement) ⇒ Unit): Unit

def walkParentTreeStatementsUntilRootScope(func: (TreeStatement) ⇒ Unit): Unit

def walkRemapDrivingExpressions(func: (Expression) ⇒ Expression): Unit

def walkRemapExpressions(func: (Expression) ⇒ Expression): Unit

def wrapCast[T <: BaseType](result: T, node: Cast): T

def xorR: Bool

Logical XOR of all bits

def |(right: UInt): UInt

Logical OR operator

def |<<(that: UInt): UInt

Logical shift left (output width == input width)

def |<<(that: Int): UInt

Logical shift left (output width == input width)

def |>>(that: UInt): UInt

Logical shift Right (output width == input width)

def |>>(that: Int): UInt

Logical shift right (output width = input width)

def asDirectionLess(): UInt.this.type