Bits
Related Doc:
package core
Used to know the data type of the children class of BitVector
Concatenation between two Bits
Concatenation between two Bits
a Bits to append
a new Bits of width (w(this) + w(right))
val myBits2 = bits1 ## bits2
Concatenation between two data
Concatenation between two data
Logical AND operator
Assign a range value to a Bits
Assign a range value to a Bits
The first range value
Others range values
core.io.interrupt = (0 -> uartCtrl.io.interrupt, 1 -> timerCtrl.io.interrupt, default -> false)
Assign a data to this
Assign a data to this
Logical shift left (output width will increase of w(this) + max(that) bits
Logical shift left (output width will increase)
Logical shift left (output width will increase)
the number of shift
a Bits of width : w(this) + that bits
val result = myBits << 4
Auto connection between two data
Auto connection between two data
BitVector is not equal to MaskedLiteral
BitVector is not equal to MaskedLiteral
Comparison between two data
Comparison between two data
Compare a BitVector with a MaskedLiteral (M"110--0")
Compare a BitVector with a MaskedLiteral (M"110--0")
the maskedLiteral
a Bool data containing the result of the comparison
val myBool = myBits === M"0-1"
Logical shift right (output width == input width)
Logical shift right (output width will decrease)
Logical shift right (output width will decrease)
the number of shift
a Bits of width : w(this) - that bits
val result = myBits >> 4
Use as \= to have the same behavioral thant VHDL variable
Use as \= to have the same behavioral thant VHDL variable
Logical XOR operator
Allow a data to be overrided
Allow a data to be overrided
Logical AND of all bits
Logical AND of all bits
Return a range of bits at offset and of width bitCount
Return a range of bits at offset and of width bitCount
Return the bit at index bitId
Return the bit at index bitId
Return a range of bits
Return a range of bits
val myBool = myBits(3 downto 1)
Cast data to Bits
Cast the BitVector into a Vector of Bool
set a data as inout
Set a data as input
Set a data as output
Cast a Bits to a SInt
Cast a Bits to a SInt
a SInt data
val mySInt = myBits.asSInt
Cast a Bits to an UInt
Cast a Bits to an UInt
an UInt data
val myUInt = myBits.asUInt
Clear all bits
Clear all bits
Set a default value to a data
Set a default value to a data
flip the direction of the data
flip the direction of the data
Generate this if condition is true
Generate this if condition is true
Return the width of the data
Get current component with all parents
Get current component with all parents
Return the width
Return the width
Create a data set to 0
Does the base type have initial value
Does the base type have initial value
Return the upper bound
Return the upper bound
Set inital value to a data
Set inital value to a data
Is the baseType a node
Is the baseType a node
Is the basetype using reset signal
Is the basetype using reset signal
Is the basetype using soft reset signal
Is the basetype using soft reset signal
Check if the baseType is vital
Check if the baseType is vital
Return the least significant bit
Return the least significant bit
Return the most significant bit
Return the most significant bit
Extract a range of bits of the BitVector
Extract a range of bits of the BitVector
Extract a range of bits of the BitVector
Extract a range of bits of the BitVector
Extract a bit of the BitVector
Extract a bit of the BitVector
Extract a bit of the BitVector
Extract a bit of the BitVector
Logical OR of all bits
Logical OR of all bits
Pull a signal to the top level (use for debugging)
Pull a signal to the top level (use for debugging)
Usefull for register that doesn't need a reset value in RTL, but need a randome value for simulation (avoid x-propagation)
Usefull for register that doesn't need a reset value in RTL, but need a randome value for simulation (avoid x-propagation)
Return the range
Return the range
Remove all assignements of the base type
Resize the bitVector to width
Resize by keeping MSB at the same place If the final size is bigger than the original size, the leftmost bits are filled with zeroes if the final size is smaller, only width MSB are kept
Resize by keeping MSB at the same place If the final size is bigger than the original size, the leftmost bits are filled with zeroes if the final size is smaller, only width MSB are kept
Final width
Resized bits vector
Resized data regarding target
Resized data regarding target
Left rotation of that bits
Left rotation of that Bits
Left rotation of that Bits
Right rotation of that bits
Right rotation of that Bits
Right rotation of that Bits
Set all bits
Set all bits to value
Set all bits to value
Set all bits to value
Set all bits to value
Set baseType to Combinatorial
remove the direction (in,out,inout) to a data
Set baseType to reg
Set baseType to Node
Set baseType to Node
Set the baseType to vital
Set the baseType to vital
Set the width of the BitVector
Set the width of the BitVector
the width of the data
the BitVector of a given size
Split the BitVector into slice of x bits * @example
Split the BitVector into slice of x bits * @example
val res = myBits.subdiviedIn(3 bits)
the width of the slice
a Vector of slices
Split the BitVector into x slice
Split the BitVector into x slice
the width of the slice
a Vector of slices
val res = myBits.subdiviedIn(3 slices)
Cast a Bits to a given data type
Cast a Bits to a given data type
the wanted data type
a new data type assign with the value of Bits
val myUInt = myBits.toDataType(UInt)
Inverse bitwise operator
Logical XOR of all bits
Logical XOR of all bits
Logical OR operator
Logical shift left (output width == input width)
Logical shift left (output width == input width)
Logical shift Right (output width == input width)
Logical shift right (output width == input width)
Logical shift right (output width == input width)
the number of shift
a Bits of width : w(this)
val result = myBits |>> 4
The Bits type corresponds to a vector of bits that does not convey any arithmetic meaning.
Bits Documentation