!==
SpinalEnumCraft
##
Bits
Data
#=
SimBitVectorPimper
SimBoolPimper
SimEnumPimper
%
BitCount
HertzNumber
Num
PhysicalNumber
SInt
TimeNumber
UInt
&
Bits
BitwiseOp
Bool
SInt
UInt
&&
Bool
*
BitCount
HertzNumber
Num
PhysicalNumber
QFormat
SFix
SInt
TimeNumber
UFix
UInt
+
BitCount
HertzNumber
Num
PhysicalNumber
QFormat
SFix
SInt
TimeNumber
UFix
UInt
AssignedBits
+^
Num
SInt
UInt
+|
Num
SInt
UInt
-
BitCount
HertzNumber
Num
PhysicalNumber
QFormat
SFix
SInt
TimeNumber
UFix
UInt
-^
Num
SInt
UInt
-|
Num
SInt
UInt
/
BitCount
HertzNumber
Num
PhysicalNumber
SInt
TimeNumber
UInt
:=
Bits
DataPrimitives
SFix
SInt
SpinalEnumCraft
UFix
UInt
<
Num
SFix
SInt
UFix
UInt
<<
Bits
Num
QFormat
SFix
SInt
UFix
UInt
<<|
SFix
UFix
<=
Num
SFix
SInt
UFix
UInt
<>
DataPrimitives
=/=
BitVector
Bool
DataPrimitives
MaskedBoolean
MaskedLiteral
SpinalEnumCraft
SpinalEnumElement
===
BitVector
Bool
DataPrimitives
MaskedBoolean
MaskedLiteral
SpinalEnumCraft
SpinalEnumElement
>
Num
SFix
SInt
UFix
UInt
>=
Num
SFix
SInt
UFix
UInt
>>
Bits
Num
QFormat
SFix
SInt
UFix
UInt
>>|
SFix
UFix
?
Bool
@@
SInt
UInt
\
DataPrimitives
^
Bits
BitwiseOp
Bool
SInt
UInt
_additionalIncludeDir
SpinalSimConfig
_additionalRtlPath
SpinalSimConfig
_backend
SpinalSimConfig
_data
DataPimper
UInt
_default
FixPointProperty
ScopeProperty
_fixEntry
SInt
UInt
_optimisationLevel
SpinalSimConfig
_referenceSet
ComponentEmitterVerilog
ComponentEmitterVhdl
_referenceSetEnabled
ComponentEmitterVerilog
ComponentEmitterVhdl
_rtlGen
SimConfigLegacy
_simulatorFlags
SpinalSimConfig
_spinalConfig
SimConfigLegacy
SpinalSimConfig
_spinalReport
SimConfigLegacy
_spinalTags
SpinalTagReady
_waveDepth
SpinalSimConfig
_waveFormat
SpinalSimConfig
_widths
Mem
_withCoverage
SpinalSimConfig
_workspaceName
SpinalSimConfig
_workspacePath
SpinalSimConfig
|
Bits
BitwiseOp
Bool
MuxBuilder
MuxBuilderEnum
SInt
UInt
|<<
Bits
SInt
UInt
|>>
Bits
SInt
UInt
||
Bool