Mem

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

var _spinalTags: LinkedHashSet[SpinalTag]

val _widths: Vector[Int]

def addAttribute(attribute: Attribute): Mem.this.type

def addAttribute(name: String, value: Int): Mem.this.type

def addAttribute(name: String, value: String): Mem.this.type

def addAttribute(name: String): Mem.this.type

def addTag[T <: SpinalTag](spinalTag: T): Mem.this.type

def addTags[T <: SpinalTag](tags: Iterable[T]): Mem.this.type

val addressType: HardType[UInt]

def addressWidth: Int

var algoIncrementale: Int

var algoInt: Int

def apply(address: UInt): T

final def asInstanceOf[T0]: T0

def byteCount: Int

def clone(): AnyRef

def component: Component

def dlcAppend(that: MemPortStatement): Mem.this.type

def dlcForeach[T >: MemPortStatement](func: (T) ⇒ Unit): Unit

def dlcHasOnlyOne: Boolean

var dlcHead: MemPortStatement

def dlcIsEmpty: Boolean

var dlcLast: MemPortStatement

def dlcPrepend(that: MemPortStatement): Mem.this.type

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

def existsTag(cond: (SpinalTag) ⇒ Boolean): Boolean

def filterTag(cond: (SpinalTag) ⇒ Boolean): Iterable[SpinalTag]

def findTag(cond: (SpinalTag) ⇒ Boolean): Option[SpinalTag]

var forceMemToBlackboxTranslation: Boolean

def foreachClockDomain(func: (ClockDomain) ⇒ Unit): Unit

def foreachDrivingExpression(func: (Expression) ⇒ Unit): Unit

def foreachExpression(func: (Expression) ⇒ Unit): Unit

def foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit

def foreachStatements(func: (MemPortStatement) ⇒ Unit): Unit

def foreachTag(body: (SpinalTag) ⇒ Unit): Unit

def generateAsBlackBox(): Mem.this.type

final def getClass(): Class[_]

def getComponent(): Component

def getComponents(): Seq[Component]

Get current component with all parents

def getDisplayName(): String

def getInstanceCounter: Int

def getMode: Byte

def getName(default: String): String

def getName(): String

def getPartialName(): String

def getRefOwnersChain(): List[Any]

def getScalaLocationLong: String

def getScalaLocationShort: String

def getScalaTrace(): Throwable

def getTag[T <: SpinalTag](clazz: Class[T]): Option[T]

def getTags(): LinkedHashSet[SpinalTag]

val getWidth: Int

val globalData: GlobalData

def hasOnlyOneStatement: Boolean

def hasTag[T <: SpinalTag](clazz: Class[T]): Boolean

def hasTag(spinalTag: SpinalTag): Boolean

def hashCode(): Int

def head: MemPortStatement

def init(initialContent: Seq[T]): Mem.this.type

def initBigInt(initialContent: Seq[BigInt], allowNegative: Boolean = false): Mem.this.type

var initialContent: Array[BigInt]

def insertNext(s: Statement): Unit

def instanceAttributes(language: Language): Iterable[Attribute]

def instanceAttributes: Iterable[Attribute]

def isCompletelyUnnamed: Boolean

def isEmptyOfTag: Boolean

final def isInstanceOf[T0]: Boolean

def isNamed: Boolean

def isPriorityApplicable(namePriority: Byte): Boolean

def isUnnamed: Boolean

var lastScopeStatement: Statement

var name: String

var nameableRef: Nameable

final def ne(arg0: AnyRef): Boolean

var nextScopeStatement: Statement

def normalizeInputs: Unit

final def notify(): Unit

final def notifyAll(): Unit

def onEachAttributes(doIt: (Attribute) ⇒ Unit): Unit

def overrideLocalName(name: String): Mem.this.type

var parentScope: ScopeStatement

def randBoot(): Mem.this.type

def readAsync(address: UInt, readUnderWrite: ReadUnderWritePolicy = dontCare): T

def readAsyncImpl(address: UInt, data: Data, readUnderWrite: ReadUnderWritePolicy = dontCare, allowMixedWidth: Boolean): Unit

def readSync(address: UInt, enable: Bool = null, readUnderWrite: ReadUnderWritePolicy = dontCare, clockCrossing: Boolean = false): T

def readSyncImpl(address: UInt, data: Data, enable: Bool = null, readUnderWrite: ReadUnderWritePolicy = dontCare, clockCrossing: Boolean = false, allowMixedWidth: Boolean = false): Unit

def readSyncMixedWidth(address: UInt, data: Data, enable: Bool = null, readUnderWrite: ReadUnderWritePolicy = dontCare, clockCrossing: Boolean = false): Unit

def readWriteSync(address: UInt, data: T, enable: Bool, write: Bool, mask: Bits = null, readUnderWrite: ReadUnderWritePolicy = dontCare, clockCrossing: Boolean = false): T

def readWriteSyncImpl[U <: Data](address: UInt, data: U, enable: Bool, write: Bool, mask: Bits = null, readUnderWrite: ReadUnderWritePolicy = dontCare, clockCrossing: Boolean = false, allowMixedWidth: Boolean = false): U

def readWriteSyncMixedWidth[U <: Data](address: UInt, data: U, enable: Bool, write: Bool, mask: Bits = null, readUnderWrite: ReadUnderWritePolicy = dontCare, clockCrossing: Boolean = false): U

var refOwner: RefOwnerType

def reflectNames(): Unit

def remapDrivingExpressions(func: (Expression) ⇒ Expression): Unit

def remapExpressions(func: (Expression) ⇒ Expression): Unit

def removeStatement(): Unit

def removeStatementFromScope(): Unit

def removeTag(spinalTag: SpinalTag): Mem.this.type

def removeTags(tags: Iterable[SpinalTag]): Mem.this.type

def rootScopeStatement: ScopeStatement

def setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): Mem.this.type

def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): Mem.this.type

def setCompositeName(nameable: Nameable, postfix: String): Mem.this.type

def setCompositeName(nameable: Nameable, namePriority: Byte): Mem.this.type

def setCompositeName(nameable: Nameable, weak: Boolean): Mem.this.type

def setCompositeName(nameable: Nameable): Mem.this.type

def setName(name: String, namePriority: Byte): Mem.this.type

def setName(name: String, weak: Boolean): Mem.this.type

def setName(name: String): Mem.this.type

def setNameAsWeak(): Mem.this.type

def setPartialName(name: String, namePriority: Byte): Mem.this.type

def setPartialName(name: String, weak: Boolean): Mem.this.type

def setPartialName(owner: Nameable, name: String, namePriority: Byte): Mem.this.type

def setPartialName(owner: Nameable, name: String, weak: Boolean): Mem.this.type

def setPartialName(name: String): Mem.this.type

def setPartialName(owner: Nameable, name: String): Mem.this.type

def setRefOwner(that: Any): Unit

def setScalaLocated(source: ScalaLocated): Mem.this.type

def setTechnology(tech: MemTechnologyKind): Unit

def setWeakName(name: String): Mem.this.type

def spinalTags: LinkedHashSet[SpinalTag]

def stabilized(func: (Expression) ⇒ Expression, seed: Expression): Expression

final def synchronized[T0](arg0: ⇒ T0): T0

var technology: MemTechnologyKind

def toString(): String

def toStringMultiLine(): String

def unsetName(): Mem.this.type

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

final def wait(): Unit

def walkDrivingExpressions(func: (Expression) ⇒ Unit): Unit

def walkExpression(func: (Expression) ⇒ Unit): Unit

def walkExpressionPostorder(func: (Expression) ⇒ Unit): Unit

def walkParentTreeStatements(func: (TreeStatement) ⇒ Unit): Unit

def walkParentTreeStatementsUntilRootScope(func: (TreeStatement) ⇒ Unit): Unit

def walkRemapDrivingExpressions(func: (Expression) ⇒ Expression): Unit

def walkRemapExpressions(func: (Expression) ⇒ Expression): Unit

val width: Int

val wordCount: Int

val wordType: HardType[T]

def write(address: UInt, data: T, enable: Bool = null, mask: Bits = null): Unit

def writeImpl(address: UInt, data: Data, enable: Bool = null, mask: Bits = null, allowMixedWidth: Boolean = false): Unit

def writeMixedWidth(address: UInt, data: Data, enable: Bool = null, mask: Bits = null): Unit

def finalize(): Unit

def readSyncCC(address: UInt, enable: Bool = True, readUnderWrite: ReadUnderWritePolicy = dontCare): T