ComponentEmitterVhdl

Instance Constructors

new ComponentEmitterVhdl(c: Component, vhdlBase: VhdlBase, algoIdIncrementalBase: Int, mergeAsyncProcess: Boolean, asyncResetCombSensitivity: Boolean, anonymSignalPrefix: String, emitedComponentRef: ConcurrentHashMap[Component, Component], pc: PhaseContext, spinalConfig: SpinalConfig)

Type Members

class AsyncProcess extends AnyRef

Definition Classes
ComponentEmitter
class SyncGroup extends AnyRef

Definition Classes
ComponentEmitter

Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
val _referenceSet: LinkedHashSet[String]
var _referenceSetEnabled: Boolean
def accessBitVectorFixed(e: BitVectorRangedAccessFixed): String
def accessBitVectorFloating(e: BitVectorRangedAccessFloating): String
def accessBoolFixed(e: BitVectorBitAccessFixed): String
def accessBoolFloating(e: BitVectorBitAccessFloating): String
val algoIdIncrementalBase: Int

Definition Classes
ComponentEmitterVhdl → ComponentEmitter
var algoIdIncrementalOffset: Int

Definition Classes
ComponentEmitter
def allocateAlgoIncrementale(): Int

Definition Classes
ComponentEmitter
val analogs: ArrayBuffer[BaseType]

Definition Classes
ComponentEmitter
final def asInstanceOf[T0]: T0

Definition Classes
Any
def binaryOperatorImplAsFunction(vhd: String)(e: BinaryOperator): String
def blackBoxReplaceTypeRegardingTag(b: BlackBox, str: String): String
def boolLiteralImpl(e: BoolLiteral): String
val c: Component
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@HotSpotIntrinsicCandidate() @throws( ... )
def commentTagsToString(host: SpinalTagReady, comment: String): String

Definition Classes
ComponentEmitter
def component: Component

Definition Classes
ComponentEmitterVhdl → ComponentEmitter
def cutLongExpressions(): Unit

Definition Classes
ComponentEmitter
val declarations: StringBuilder
def dispatchExpression(e: Expression): String
def elaborate(): Unit

Definition Classes
ComponentEmitter
def emitAnalogs(): Unit
def emitArchitecture(): Unit
def emitAssignedExpression(that: Expression): String
def emitAssignment(assignment: AssignmentStatement, tab: String, assignmentKind: String): String
def emitAsynchronous(process: AsyncProcess): Unit
def emitAttributes(node: String, attributes: Iterable[Attribute], vhdlType: String, ret: StringBuilder, postfix: String): Unit
def emitAttributes(node: DeclarationStatement, attributes: Iterable[Attribute], vhdlType: String, ret: StringBuilder, postfix: String = ""): Unit
def emitAttributesDef(): Unit
def emitBitsLiteral(e: BitsLiteral): String
def emitBlackBoxComponent(component: BlackBox): Unit
def emitBlackBoxComponents(): Unit
def emitClockedProcess(emitRegsLogic: (String, StringBuilder) ⇒ Unit, emitRegsInitialValue: (String, StringBuilder) ⇒ Unit, b: StringBuilder, clockDomain: ClockDomain, withReset: Boolean): Unit
def emitEntity(): Unit
def emitEnumLiteralWrap(e: EnumLiteral[_ <: SpinalEnum]): String
def emitEnumPoison(e: Expression): String
def emitExpression(that: Expression): String
def emitExpressionNoWrappeForFirstOne(that: Expression): String
def emitLeafStatements(statements: ArrayBuffer[LeafStatement], statementIndexInit: Int, scope: ScopeStatement, assignmentKind: String, b: StringBuilder, tab: String): Int
def emitLibrary(ret: StringBuilder): Unit
def emitMem(mem: Mem[_]): Unit
def emitMems(mems: ArrayBuffer[Mem[_]]): Unit
def emitMuxes(): Unit
def emitReference(that: DeclarationStatement, sensitive: Boolean): String
def emitReferenceNoOverrides(that: DeclarationStatement): String
def emitSIntLiteral(e: SIntLiteral): String
def emitSignals(): Unit
def emitSubComponents(openSubIo: HashSet[BaseType]): Unit
def emitSynchronous(component: Component, group: SyncGroup): Unit
def emitUIntLiteral(e: UIntLiteral): String
def enumEgualsImpl(eguals: Boolean)(e: BinaryOperator with EnumEncoded): String
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(arg0: Any): Boolean

Definition Classes
AnyRef → Any
val expressionToWrap: LinkedHashSet[Expression]

Definition Classes
ComponentEmitter
def getBaseTypeSignalInitialisation(signal: BaseType): String
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
Annotations
@HotSpotIntrinsicCandidate()
def getOrDefault[X, Y](map: ConcurrentHashMap[X, Y], key: X, default: Y): Y

Definition Classes
ComponentEmitter
def getTrace(): ComponentEmitterTrace
def hashCode(): Int

Definition Classes
AnyRef → Any
Annotations
@HotSpotIntrinsicCandidate()
val initials: ArrayBuffer[LeafStatement]

Definition Classes
ComponentEmitter
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
def isSubComponentInputBinded(data: BaseType): Expression

Definition Classes
ComponentEmitter
val logics: StringBuilder
var memBitsMaskKind: MemBitsMaskKind
val mems: ArrayBuffer[Mem[_]]

Definition Classes
ComponentEmitter
val mergeAsyncProcess: Boolean

Definition Classes
ComponentEmitterVhdl → ComponentEmitter
def moduloImpl(e: Mod): String
val multiplexersPerSelect: LinkedHashMap[(Expression with WidthProvider, Int), ArrayBuffer[Multiplexer]]

Definition Classes
ComponentEmitter
def muxImplAsFunction(vhd: String)(e: BinaryMultiplexer): String
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
final def notify(): Unit

Definition Classes
AnyRef
Annotations
@HotSpotIntrinsicCandidate()
final def notifyAll(): Unit

Definition Classes
AnyRef
Annotations
@HotSpotIntrinsicCandidate()
def opImplAsCast(vhd: String)(e: Cast): String
val openSubIo: HashSet[BaseType]

Definition Classes
ComponentEmitter
def operatorImplAsBinaryOperator(vhd: String)(e: BinaryOperator): String
def operatorImplAsBinaryOperatorStdCast(vhd: String)(e: BinaryOperator): String
def operatorImplAsBitsToEnum(e: CastBitsToEnum): String
def operatorImplAsEnumToBits(e: CastEnumToBits): String
def operatorImplAsEnumToEnum(e: CastEnumToEnum): String
def operatorImplAsUnaryOperator(vhd: String)(e: UnaryOperator): String
val outputsToBufferize: LinkedHashSet[BaseType]

Definition Classes
ComponentEmitter
val portMaps: ArrayBuffer[String]
val processes: LinkedHashSet[AsyncProcess]

Definition Classes
ComponentEmitter
def readedOutputWrapEnable: Boolean

Definition Classes
ComponentEmitterVhdl → ComponentEmitter
def refImpl(e: BaseType): String
def referenceSetAdd(str: String): Unit
def referenceSetPause(): Unit
def referenceSetResume(): Unit
def referenceSetSorted(): LinkedHashSet[String]
def referenceSetStart(): Unit
def referenceSetStop(): Unit
val referencesOverrides: HashMap[Nameable, Any]

Definition Classes
ComponentEmitter
def resizeFunction(vhdlFunc: String)(e: Resize): String
def result: String
def shiftLeftBitsByIntFixedWidthImpl(e: ShiftLeftByIntFixedWidth): String
def shiftLeftBitsByUIntFixedWidthImpl(e: ShiftLeftByUIntFixedWidth): String
def shiftLeftByIntFixedWidthImpl(e: ShiftLeftByIntFixedWidth): String
def shiftLeftByIntImpl(e: ShiftLeftByInt): String
def shiftLeftByUIntFixedWidthImpl(e: ShiftLeftByUIntFixedWidth): String
def shiftRightBitsByIntFixedWidthImpl(e: ShiftRightByIntFixedWidth): String
def shiftRightByIntFixedWidthImpl(e: ShiftRightByIntFixedWidth): String
def shiftRightByIntImpl(e: ShiftRightByInt): String
def shiftSIntLeftByUInt(e: ShiftLeftByUInt): String
val spinalConfig: SpinalConfig

Definition Classes
ComponentEmitterVhdl → ComponentEmitter
val subComponentInputToNotBufferize: HashSet[Any]

Definition Classes
ComponentEmitter
val syncGroups: LinkedHashMap[(ClockDomain, ScopeStatement, Boolean), SyncGroup]

Definition Classes
ComponentEmitter
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
def toString(): String

Definition Classes
AnyRef → Any
def unaryOperatorImplAsFunction(vhd: String)(e: UnaryOperator): String
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
def wrapSubInput(io: BaseType): Unit

Definition Classes
ComponentEmitterVhdl → ComponentEmitter
val wrappedExpressionToName: HashMap[Expression, String]

Definition Classes
ComponentEmitter

Deprecated Value Members

def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@Deprecated @deprecated @throws( classOf[java.lang.Throwable] )
Deprecated
(Since version ) see corresponding Javadoc for more information.

Related Doc: package internals

class ComponentEmitterVhdl extends ComponentEmitter

Instance Constructors

new ComponentEmitterVhdl(c: Component, vhdlBase: VhdlBase, algoIdIncrementalBase: Int, mergeAsyncProcess: Boolean, asyncResetCombSensitivity: Boolean, anonymSignalPrefix: String, emitedComponentRef: ConcurrentHashMap[Component, Component], pc: PhaseContext, spinalConfig: SpinalConfig)

Type Members

class AsyncProcess extends AnyRef

class SyncGroup extends AnyRef

Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

val _referenceSet: LinkedHashSet[String]

var _referenceSetEnabled: Boolean

def accessBitVectorFixed(e: BitVectorRangedAccessFixed): String

def accessBitVectorFloating(e: BitVectorRangedAccessFloating): String

def accessBoolFixed(e: BitVectorBitAccessFixed): String

def accessBoolFloating(e: BitVectorBitAccessFloating): String

val algoIdIncrementalBase: Int

var algoIdIncrementalOffset: Int

def allocateAlgoIncrementale(): Int

val analogs: ArrayBuffer[BaseType]

final def asInstanceOf[T0]: T0

def binaryOperatorImplAsFunction(vhd: String)(e: BinaryOperator): String

def blackBoxReplaceTypeRegardingTag(b: BlackBox, str: String): String

def boolLiteralImpl(e: BoolLiteral): String

val c: Component

def clone(): AnyRef

def commentTagsToString(host: SpinalTagReady, comment: String): String

def component: Component

def cutLongExpressions(): Unit

val declarations: StringBuilder

def dispatchExpression(e: Expression): String

def elaborate(): Unit

def emitAnalogs(): Unit

def emitArchitecture(): Unit

def emitAssignedExpression(that: Expression): String

def emitAssignment(assignment: AssignmentStatement, tab: String, assignmentKind: String): String

def emitAsynchronous(process: AsyncProcess): Unit

def emitAttributes(node: String, attributes: Iterable[Attribute], vhdlType: String, ret: StringBuilder, postfix: String): Unit

def emitAttributes(node: DeclarationStatement, attributes: Iterable[Attribute], vhdlType: String, ret: StringBuilder, postfix: String = ""): Unit

def emitAttributesDef(): Unit

def emitBitsLiteral(e: BitsLiteral): String

def emitBlackBoxComponent(component: BlackBox): Unit

def emitBlackBoxComponents(): Unit

def emitClockedProcess(emitRegsLogic: (String, StringBuilder) ⇒ Unit, emitRegsInitialValue: (String, StringBuilder) ⇒ Unit, b: StringBuilder, clockDomain: ClockDomain, withReset: Boolean): Unit

def emitEntity(): Unit

def emitEnumLiteralWrap(e: EnumLiteral[_ <: SpinalEnum]): String

def emitEnumPoison(e: Expression): String

def emitExpression(that: Expression): String

def emitExpressionNoWrappeForFirstOne(that: Expression): String

def emitLeafStatements(statements: ArrayBuffer[LeafStatement], statementIndexInit: Int, scope: ScopeStatement, assignmentKind: String, b: StringBuilder, tab: String): Int

def emitLibrary(ret: StringBuilder): Unit

def emitMem(mem: Mem[_]): Unit

def emitMems(mems: ArrayBuffer[Mem[_]]): Unit

def emitMuxes(): Unit

def emitReference(that: DeclarationStatement, sensitive: Boolean): String

def emitReferenceNoOverrides(that: DeclarationStatement): String

def emitSIntLiteral(e: SIntLiteral): String

def emitSignals(): Unit

def emitSubComponents(openSubIo: HashSet[BaseType]): Unit

def emitSynchronous(component: Component, group: SyncGroup): Unit

def emitUIntLiteral(e: UIntLiteral): String

def enumEgualsImpl(eguals: Boolean)(e: BinaryOperator with EnumEncoded): String

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

val expressionToWrap: LinkedHashSet[Expression]

def getBaseTypeSignalInitialisation(signal: BaseType): String

final def getClass(): Class[_]

def getOrDefault[X, Y](map: ConcurrentHashMap[X, Y], key: X, default: Y): Y

def getTrace(): ComponentEmitterTrace

def hashCode(): Int

val initials: ArrayBuffer[LeafStatement]

final def isInstanceOf[T0]: Boolean

def isSubComponentInputBinded(data: BaseType): Expression

val logics: StringBuilder

var memBitsMaskKind: MemBitsMaskKind

val mems: ArrayBuffer[Mem[_]]

val mergeAsyncProcess: Boolean

def moduloImpl(e: Mod): String