Data

abstract def asBits: Bits

Cast data to Bits

abstract def assignFromBits(bits: Bits, hi: Int, low: Int): Unit

abstract def assignFromBits(bits: Bits): Unit

abstract def flatten: Seq[BaseType]

abstract def flattenLocalName: Seq[String]

abstract def freeze(): Data.this.type

abstract def getBitsWidth: Int

Return the width of the data

abstract def getZero: Data.this.type

Create a data set to 0

abstract def setAsComb(): Data.this.type

Set baseType to Combinatorial

abstract def setAsReg(): Data.this.type

Set baseType to reg

abstract def unfreeze(): Data.this.type

final def !=(arg0: Any): Boolean

def ##(right: Data): Bits

Concatenation between two data

final def ##(): Int

def #*(count: Int): Bits

final def ==(arg0: Any): Boolean

var _spinalTags: LinkedHashSet[SpinalTag]

def addAttribute(attribute: Attribute): Data.this.type

def addAttribute(name: String, value: Int): Data.this.type

def addAttribute(name: String, value: String): Data.this.type

def addAttribute(name: String): Data.this.type

def addTag[T <: SpinalTag](spinalTag: T): Data.this.type

def addTags[T <: SpinalTag](tags: Iterable[T]): Data.this.type

def allowDirectionLessIo(): Data.this.type

Allow a Data of an io Bundle to be directionless

def allowOverride(): Data.this.type

Allow a Data to be overriden

def allowPartialyAssigned(): Data.this.type

Allow a register to be partially assigned

def allowPruning(): Data.this.type

def allowSimplifyIt(): Data.this.type

def allowUnsetRegToAvoidLatch(): Data.this.type

Allow a register to have only an init (no assignments)

def as[T <: Data](dataType: HardType[T]): T

def asData: Data

def asInOut(): Data.this.type

set a data as inout

def asInput(): Data.this.type

Set a data as input

final def asInstanceOf[T0]: T0

def asOutput(): Data.this.type

Set a data as output

def assignDontCare(): Data.this.type

def assignDontCareToUnasigned(): Data.this.type

def assignFormalRandom(kind: RandomExpKind): Unit

final def assignFrom(that: AnyRef, target: AnyRef = this)(implicit loc: Location): Unit

def assignFromBits(bits: Bits, offset: Int, bitCount: BitCount): Unit

def clearAll(): Data.this.type

def clone(): Data

def component: Component

final def compositAssignFrom(that: AnyRef, target: AnyRef, kind: AnyRef)(implicit loc: Location): Unit

var compositeAssign: Assignable

def copyDirectionOfImpl(that: Data): Data.this.type

def dirString(): String

def dontSimplifyIt(): Data.this.type

final def eq(arg0: AnyRef): Boolean

def equals(obj: Any): Boolean

def existsTag(cond: (SpinalTag) ⇒ Boolean): Boolean

def filterTag(cond: (SpinalTag) ⇒ Boolean): Iterable[SpinalTag]

def findTag(cond: (SpinalTag) ⇒ Boolean): Option[SpinalTag]

def flattenForeach(body: (BaseType) ⇒ Unit): Unit

def flip(): Data.this.type

flip the direction of the data

def foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit

def foreachTag(body: (SpinalTag) ⇒ Unit): Unit

def getAheadValue(): Data.this.type

final def getClass(): Class[_]

def getComponent(): Component

def getComponents(): Seq[Component]

Get current component with all parents

def getDirection: IODirection

def getDisplayName(): String

def getInstanceCounter: Int

def getMode: Byte

def getMuxType[T <: Data](list: TraversableOnce[T]): HardType[T]

def getName(default: String): String

def getName(): String

def getPartialName(): String

def getPath(from: Component, to: Component): Seq[Component]

def getRealSource: Any

def getRealSourceNoRec: Any

def getRefOwnersChain(): List[Any]

def getRootParent: Data

def getRtlPath(separator: String = "/"): String

def getScalaLocationLong: String

def getScalaLocationShort: String

def getScalaTrace(): Throwable

def getTag[T <: SpinalTag](clazz: Class[T]): Option[T]

def getTags(): LinkedHashSet[SpinalTag]

val globalData: GlobalData

def hasTag[T <: SpinalTag](clazz: Class[T]): Boolean

def hasTag(spinalTag: SpinalTag): Boolean

def hashCode(): Int

final def initFrom(that: AnyRef, target: AnyRef = this): Unit

def instanceAttributes(language: Language): Iterable[Attribute]

def instanceAttributes: Iterable[Attribute]

def isAnalog: Boolean

def isComb: Boolean

def isCompletelyUnnamed: Boolean

def isDirectionLess: Boolean

def isEmptyOfTag: Boolean

def isInOut: Boolean

def isInput: Boolean

def isInputOrInOut: Boolean

final def isInstanceOf[T0]: Boolean

def isNamed: Boolean

def isOutput: Boolean

def isOutputOrInOut: Boolean

def isPriorityApplicable(namePriority: Byte): Boolean

def isReg: Boolean

def isRegOnAssign: Boolean

def isUnnamed: Boolean

var name: String

var nameableRef: Nameable

final def ne(arg0: AnyRef): Boolean

def noBackendCombMerge(): Data.this.type

Put the combinatorial logic driving this signal in a separate process

def noCombLoopCheck(): Data.this.type

Disable combinatorial loop checking for this Data

final def notify(): Unit

final def notifyAll(): Unit

def onEachAttributes(doIt: (Attribute) ⇒ Unit): Unit

def overrideLocalName(name: String): Data.this.type

var parent: Data

var parentScope: ScopeStatement

def pull(propagateName: Boolean): Data.this.type

def pull(): Data.this.type

Pull a signal to the top level (use for debugging)

def purify(): Data.this.type

def randBoot(u: Unit): Data.this.type

Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)

var refOwner: RefOwnerType

def reflectNames(): Unit

def removeAssignments(data: Boolean = true, init: Boolean = true, initial: Boolean = true): Data.this.type

def removeDataAssignments(): Data.this.type

def removeInitAssignments(): Data.this.type

def removeTag(spinalTag: SpinalTag): Data.this.type

def removeTags(tags: Iterable[SpinalTag]): Data.this.type

def resized: Data.this.type

Resized data regarding target

var scalaTrace: Throwable

def setAll(): Data.this.type

def setAsAnalog(): Data.this.type

def setAsDirectionLess(): Data.this.type

remove the direction (in,out,inout) to a data

def setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): Data.this.type

def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): Data.this.type

def setCompositeName(nameable: Nameable, postfix: String): Data.this.type

def setCompositeName(nameable: Nameable, namePriority: Byte): Data.this.type

def setCompositeName(nameable: Nameable, weak: Boolean): Data.this.type

def setCompositeName(nameable: Nameable): Data.this.type

def setLambdaName(isNameBody: ⇒ Boolean)(nameGen: ⇒ String): Data.this.type

def setName(name: String, namePriority: Byte): Data.this.type

def setName(name: String, weak: Boolean): Data.this.type

def setName(name: String): Data.this.type

def setNameAsWeak(): Data.this.type

def setPartialName(name: String, namePriority: Byte, owner: Any): Data.this.type

def setPartialName(name: String, namePriority: Byte): Data.this.type

def setPartialName(name: String, weak: Boolean): Data.this.type

def setPartialName(owner: Nameable, name: String, namePriority: Byte): Data.this.type

def setPartialName(owner: Nameable, name: String, weak: Boolean): Data.this.type

def setPartialName(name: String): Data.this.type

def setPartialName(owner: Nameable, name: String): Data.this.type

def setPartialName(owner: Nameable): Data.this.type

def setRefOwner(that: Any): Unit

def setScalaLocated(source: ScalaLocated): Data.this.type

def setWeakName(name: String): Data.this.type

def spinalTags: LinkedHashSet[SpinalTag]

final def synchronized[T0](arg0: ⇒ T0): T0

def toIo(): Data.this.type

def toMuxInput[T <: Data](muxOutput: T): T

def toString(): String

def unsetName(): Data.this.type

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

final def wait(): Unit

def wrapNext(): Data.this.type

def asDirectionLess(): Data.this.type

def finalize(): Unit

def genIf(cond: Boolean): Data.this.type

Generate this if condition is true