spinal.lib.cpu.riscv.impl

RiscvCore

Related Docs: object RiscvCore | package impl

class RiscvCore extends Component

Linear Supertypes
Component, Stackable, DelayedInit, ScalaLocated, NameableByComponent, GlobalDataUser, Nameable, OwnableRef, AnyRef, Any
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Inherited
  1. RiscvCore
  2. Component
  3. Stackable
  4. DelayedInit
  5. ScalaLocated
  6. NameableByComponent
  7. GlobalDataUser
  8. Nameable
  9. OwnableRef
  10. AnyRef
  11. Any
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  1. Public
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Instance Constructors

  1. new RiscvCore()(implicit c: RiscvCoreConfig)

Type Members

  1. case class PrePopTask extends Product with Serializable

    Definition Classes
    Component

  2. type RefOwnerType = Component

    Definition Classes
    Component → OwnableRef

Value Members

  1. final def !=(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any

  2. final def ##(): Int

    Definition Classes
    AnyRef → Any

  3. final def ==(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any

  4. def addPrePopTask(task: () ⇒ Unit): ArrayBuffer[PrePopTask]

    Definition Classes
    Component

  5. lazy val applyExtensionTags: Unit

  6. final def asInstanceOf[T0]: T0

    Definition Classes
    Any

  7. val branchArbiter: Area

  8. val brancheCache: Mem[BranchPredictorLine]

  9. implicit val c: RiscvCoreConfig

  10. val children: ArrayBuffer[Component]

    Definition Classes
    Component

  11. val clockDomain: ClockDomain

    Definition Classes
    Component

  12. def clone(): AnyRef

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  13. val dCmd: Stream[CoreDataCmd]

  14. val dRsp: Stream[Bits]

  15. val dataBusKind: DataBusKind

  16. val decode: Area { ... /* 23 definitions in type refinement */ }

  17. var definitionName: String

    Definition Classes
    Component

  18. def delayedInit(body: ⇒ Unit): Unit

    Definition Classes
    Component → DelayedInit

  19. final def eq(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  20. def equals(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any

  21. val execute0: Area { ... /* 11 definitions in type refinement */ }

  22. val execute1: Area { ... /* 9 definitions in type refinement */ }

  23. val fetch: Area { ... /* 6 definitions in type refinement */ }

  24. def finalize(): Unit

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )

  25. def forEachNameables(doThat: (Any) ⇒ Unit): Unit

    Definition Classes
    Nameable

  26. def getAdditionalNodesRoot: Set[Node]

    Definition Classes
    Component

  27. def getAllIo: Set[BaseType]

    Definition Classes
    Component

  28. final def getClass(): Class[_]

    Definition Classes
    AnyRef → Any

  29. def getDisplayName(): String

    Definition Classes
    Component → Nameable

  30. def getGroupedIO(ioBundleBypass: Boolean): Seq[Data]

    Definition Classes
    Component

  31. def getInstructionCtrl(instruction: Bits): InstructionCtrl

  32. def getName(): String

    Definition Classes
    NameableByComponent → Nameable

  33. def getName(default: String): String

    Definition Classes
    Nameable

  34. def getOrdredNodeIo: List[BaseType]

    Definition Classes
    Component

  35. def getParentsPath(sep: String): String

    Definition Classes
    Component

  36. def getPath(sep: String): String

    Definition Classes
    Component

  37. def getRefOwnersChain(): List[Any]

    Definition Classes
    OwnableRef

  38. def getScalaLocationLong: String

    Definition Classes
    ScalaLocated

  39. def getScalaLocationShort: String

    Definition Classes
    ScalaLocated

  40. val globalData: GlobalData

    Definition Classes
    GlobalDataUser

  41. def hashCode(): Int

    Definition Classes
    AnyRef → Any

  42. val hazardTracker: Area { ... /* 6 definitions in type refinement */ }

  43. val iCmd: Stream[CoreInstructionCmd]

  44. val iRsp: Stream[CoreInstructionRsp]

  45. val irqExceptionMask: Int

  46. val irqUsages: HashMap[Int, IrqUsage]

  47. val irqWidth: Int

  48. final def isInstanceOf[T0]: Boolean

    Definition Classes
    Any

  49. def isNamed: Boolean

    Definition Classes
    Nameable

  50. def isUnnamed: Boolean

    Definition Classes
    Nameable

  51. def nameElements(): Unit

    Definition Classes
    Component

  52. final def ne(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  53. val noDataRspStallLogic: Any

  54. def noIoPrefix(): RiscvCore.this.type

    Definition Classes
    Component

  55. var nodes: ArrayBuffer[Node]

    Definition Classes
    Component

  56. final def notify(): Unit

    Definition Classes
    AnyRef

  57. final def notifyAll(): Unit

    Definition Classes
    AnyRef

  58. val parent: Component

    Definition Classes
    Component

  59. def parents(of: Component, list: List[Component]): List[Component]

    Definition Classes
    Component

  60. val performanceCounters: Area { ... /* 6 definitions in type refinement */ }

  61. def postPopEvent(): Unit

    Definition Classes
    Stackable

  62. def postPushEvent(): Unit

    Definition Classes
    Component → Stackable

  63. def prePop(): Unit

    Definition Classes
    Component

  64. def prePopEvent(): Unit

    Definition Classes
    Component → Stackable

  65. val prefetch: Area { ... /* 6 definitions in type refinement */ }

  66. var refOwner: RefOwnerType

    Definition Classes
    OwnableRef

  67. val regFile: Mem[Bits]

  68. def rework[T](gen: ⇒ T): T

    Definition Classes
    Component

  69. def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): RiscvCore.this.type

    Definition Classes
    Nameable

  70. def setCompositeName(nameable: Nameable, postfix: String): RiscvCore.this.type

    Definition Classes
    Nameable

  71. def setCompositeName(nameable: Nameable, weak: Boolean): RiscvCore.this.type

    Definition Classes
    Nameable

  72. def setCompositeName(nameable: Nameable): RiscvCore.this.type

    Definition Classes
    Nameable

  73. def setDefinitionName(name: String): RiscvCore.this.type

    Definition Classes
    Component

  74. def setName(name: String, weak: Boolean): RiscvCore.this.type

    Definition Classes
    Nameable

  75. def setPartialName(name: String, weak: Boolean): RiscvCore.this.type

    Definition Classes
    Nameable

  76. def setPartialName(owner: Nameable, name: String, weak: Boolean): RiscvCore.this.type

    Definition Classes
    Nameable

  77. def setPartialName(name: String): RiscvCore.this.type

    Definition Classes
    Nameable

  78. def setPartialName(owner: Nameable, name: String): RiscvCore.this.type

    Definition Classes
    Nameable

  79. def setRefOwner(that: Any): Unit

    Definition Classes
    OwnableRef

  80. def setWeakName(name: String): RiscvCore.this.type

    Definition Classes
    Nameable

  81. final def synchronized[T0](arg0: ⇒ T0): T0

    Definition Classes
    AnyRef

  82. def toString(): String

    Definition Classes
    Nameable → AnyRef → Any

  83. def unsetName(): Unit

    Definition Classes
    Nameable

  84. val userCache: Map[AnyRef, Map[AnyRef, AnyRef]]

    Definition Classes
    Component

  85. final def wait(): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  86. final def wait(arg0: Long, arg1: Int): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  87. final def wait(arg0: Long): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  88. val writeBack: Area { ... /* 12 definitions in type refinement */ }

  89. val writeBackBuffer: Area { val inInst: spinal.lib.Stream[spinal.lib.cpu.riscv.impl.CoreWriteBack0Output] }

Inherited from Component

Inherited from Stackable

Inherited from DelayedInit

Inherited from ScalaLocated

Inherited from NameableByComponent

Inherited from GlobalDataUser

Inherited from Nameable

Inherited from OwnableRef

Inherited from AnyRef

Inherited from Any

Ungrouped