BusSlaveFactoryDelayed

abstract def build(): Unit

In this function you have to define the read/write logic thanks to element, elementsPerAddress and elementsPerRangeAddress This is the only thing with def busDataWidth that should be implement by class that extends BusSlaveFactoryDelay

abstract def busDataWidth: Int

Return the data width of the bus

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

var _config: BusSlaveFactoryConfig

Configuration of the BusSlaveFactory

final def asInstanceOf[T0]: T0

def clone(): AnyRef

var component: Component

def createAndDriveFlow[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): Flow[T]

Create a writable Flow register of type dataType at address and placed at bitOffset in the word

def createReadWrite[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): T

Create a read write register of type dataType at address and placed at bitOffset in the word

def createWriteOnly[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): T

Create a write only register of type dataType at address and placed at bitOffset in the word

def doBitsAccumulationAndClearOnRead(that: Bits, address: BigInt, bitOffset: Int = 0): Unit

Instanciate an internal register which at each cycle do : reg := reg | that Then when a read occur, the register is cleared.

def drive[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T

Drive that with a register writable at address placed at bitOffset in the word

def driveAndRead[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T

Drive that with a register writable and readable at address placed at bitOffset in the word

def driveFlow[T <: Data](that: Flow[T], address: BigInt, bitOffset: Int = 0): Unit

Emit on that a transaction when a write happen at address by using data placed at bitOffset in the word

val elements: ArrayBuffer[BusSlaveFactoryElement]

Contains all elements created

val elementsPerAddress: HashMap[BigInt, ArrayBuffer[BusSlaveFactoryElement]]

Contains all elements related to an address

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

def finalize(): Unit

def forEachNameables(doThat: (Any) ⇒ Unit): Unit

final def getClass(): Class[_]

def getConfig: BusSlaveFactoryConfig

def getDisplayName(): String

def getInstanceCounter: Int

def getName(default: String): String

def getName(): String

def getRefOwnersChain(): List[Any]

def getScalaLocationLong: String

def getScalaLocationShort: String

val globalData: GlobalData

def hashCode(): Int

final def isInstanceOf[T0]: Boolean

def isNamed: Boolean

def isReading(address: BigInt): Bool

Return true if the bus is reading

def isUnnamed: Boolean

def isWriting(address: BigInt): Bool

Return true if the bus is writing

final def ne(arg0: AnyRef): Boolean

def nonStopWrite(that: Data, bitOffset: Int = 0): Unit

Permanently assign that by the bus write data from bitOffset

final def notify(): Unit

final def notifyAll(): Unit

def onRead(address: BigInt)(doThat: ⇒ Unit): Unit

Call doThat when a read transaction occurs on address

def onReadCondition(condition: ⇒ Bool)(doThat: ⇒ Unit): Unit

Call doThat when a read transaction occurs and the condition is true

def onWrite(address: BigInt)(doThat: ⇒ Unit): Unit

Call doThat when a write transaction occurs on address

def onWriteCondition(condition: ⇒ Bool)(doThat: ⇒ Unit): Unit

Call doThat when a write transaction occurs and the condition is true

def read(that: Data, address: BigInt, bitOffset: Int = 0): Unit

When the bus read the address, fill the response with that at bitOffset

def readAndWrite(that: Data, address: BigInt, bitOffset: Int = 0): Unit

Make that readable and writable at address and placed at bitOffset in the word

def readAndWriteMultiWord(that: Data, address: BigInt): Unit

Create the memory mapping to write/read that from address

def readMultiWord(that: Data, address: BigInt): Unit

Create the memory mapping to read that from address If that is bigger than one word it extends the register on followings addresses

def readStreamNonBlocking[T <: Data](that: Stream[T], address: BigInt, validBitOffset: Int, payloadBitOffset: Int): Unit

Read that and consume the transaction when a read happen at address.

var refOwner: RefOwnerType

def reflectNames(): Unit

def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): BusSlaveFactoryDelayed.this.type

def setCompositeName(nameable: Nameable, postfix: String): BusSlaveFactoryDelayed.this.type

def setCompositeName(nameable: Nameable, weak: Boolean): BusSlaveFactoryDelayed.this.type

def setCompositeName(nameable: Nameable): BusSlaveFactoryDelayed.this.type

def setConfig(value: BusSlaveFactoryConfig): BusSlaveFactoryDelayed.this.type

def setName(name: String, weak: Boolean): BusSlaveFactoryDelayed.this.type

def setPartialName(name: String, weak: Boolean): BusSlaveFactoryDelayed.this.type

def setPartialName(owner: Nameable, name: String, weak: Boolean): BusSlaveFactoryDelayed.this.type

def setPartialName(name: String): BusSlaveFactoryDelayed.this.type

def setPartialName(owner: Nameable, name: String): BusSlaveFactoryDelayed.this.type

def setRefOwner(that: Any): Unit

def setWeakName(name: String): BusSlaveFactoryDelayed.this.type

def setWordEndianness(value: Endianness): BusSlaveFactory

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

def unsetName(): Unit

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

def wordAddressInc: Int

Address incrementation used by the read and write multi words registers

def write[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T

When the bus write the address, assign that with bus’s data from bitOffset

def writeMultiWord(that: Data, address: BigInt): Unit

Create the memory mapping to write that at address.