sim

Type Members

1. case class Axi4StreamMaster(axis: Axi4Stream, clockDomain: ClockDomain) extends Product with Serializable

   

   Simulation master for the Axi4Stream bus protocol Axi4Stream.

   Simulation master for the Axi4Stream bus protocol Axi4Stream.

   axis

   bus master to drive

   clockDomain

   clock domain to sample data on

   Example:

   1. SimConfig.compile(new Component {
        val io = new Bundle {
          val axisSlave = slave(Axi4Stream(Axi4StreamConfig(32)))
        }
        io.axisSlave.assignDontCare
      }).doSim("sample") { dut =>
        val master = Axi4StreamMaster(dut.io.axisSlave, dut.clockDomain)
        master.send(Random.nextBytes(256).toList)
      }

2. case class Axi4StreamSlave(axis: Axi4Stream, clockDomain: ClockDomain) extends Product with Serializable

   

   Simulation slave for the Axi4Stream bus protocol Axi4Stream.

   Simulation slave for the Axi4Stream bus protocol Axi4Stream.

   axis

   bus slave to drive

   clockDomain

   clock domain to sample data on

   Example:

   1. SimConfig.compile(new Component {
        val io = new Bundle {
          val axisMaster = master(Axi4Stream(Axi4StreamConfig(32)))
        }
        io.axisMaster.assignDontCare
      }).doSim("sample") { dut =>
        val slave = Axi4StreamSlave(dut.io.axisMaster, dut.clockDomain)
        val data = slave.recv()
      }

   Note

   The current implementation does not buffer unexpected transactions (i.e. bus activity when no recv has been issued). In some race conditions, this may result in incomplete captures due to the first beats being lost. Consider enqueuing a asynchronous request with the callback interface (recvCB) before issuing the triggering action.