abstract
class
RegBase extends RegSlice
Instance Constructors
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new
RegBase(name: String, addr: BigInt, doc: String, busif: BusIf, sec: Secure = null, grp: GrpTag = null)
Abstract Value Members
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abstract
def
readGenerator(): Unit
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abstract
def
setName(name: String): RegBase
Concrete Value Members
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final
def
!=(arg0: Any): Boolean
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final
def
##(): Int
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final
def
==(arg0: Any): Boolean
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def
NA(bc: BitCount): Bits
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def
RC(bc: BitCount, section: Range, resetValue: BigInt): Bits
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def
RO(bc: BitCount): Bits
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def
RS(bc: BitCount, section: Range, resetValue: BigInt): Bits
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var
Rerror: Boolean
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def
W(bc: BitCount, section: Range, resetValue: BigInt): Bits
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def
W1(bc: BitCount, section: Range, resetValue: BigInt): Bits
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def
WB(section: Range, resetValue: BigInt, accType: AccessType): Bits
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def
WBP(section: Range, resetValue: BigInt, accType: AccessType): Bits
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def
WBR(section: Range, resetValue: BigInt, accType: AccessType): Bits
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def
WC(bc: BitCount, section: Range, resetValue: BigInt): Bits
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def
WCRS(bc: BitCount, section: Range, resetValue: BigInt): Bits
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def
WRC(bc: BitCount, section: Range, resetValue: BigInt): Bits
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def
WRS(bc: BitCount, section: Range, resetValue: BigInt): Bits
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def
WS(bc: BitCount, section: Range, resetValue: BigInt): Bits
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def
WSRC(bc: BitCount, section: Range, resetValue: BigInt): Bits
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def
_RC[T <: BaseType](reg: T, section: Range): T
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def
_RO[T <: BaseType](reg: T): T
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def
_RS[T <: BaseType](reg: T, section: Range): T
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def
_W[T <: BaseType](reg: T, section: Range): T
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def
_W1[T <: BaseType](reg: T, section: Range): T
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def
_WB[T <: BaseType](reg: T, section: Range, accType: AccessType): T
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def
_WBP[T <: BaseType](reg: T, section: Range, accType: AccessType): T
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def
_WBR[T <: BaseType](reg: T, section: Range, accType: AccessType): T
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def
_WC[T <: BaseType](reg: T, section: Range): T
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def
_WCRS[T <: BaseType](reg: T, section: Range): T
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def
_WRC[T <: BaseType](reg: T, section: Range): T
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def
_WRS[T <: BaseType](reg: T, section: Range): T
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def
_WS[T <: BaseType](reg: T, section: Range): T
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def
_WSRC[T <: BaseType](reg: T, section: Range): T
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var
_name: String
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def
addBlockSignal(sig: Bool): Unit
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val
addr: BigInt
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def
allIsNA: Boolean
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final
def
asInstanceOf[T0]: T0
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-
def
checkLast: Unit
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def
clone(): AnyRef
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val
doc: String
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def
endaddr: BigInt
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final
def
eq(arg0: AnyRef): Boolean
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def
equals(arg0: Any): Boolean
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def
eventR(): Bool
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def
eventW(): Bool
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def
fieldNA(bit: Int): Unit
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def
fieldNA(pos: Int, bit: Int): Unit
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var
fieldPtr: Int
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val
fields: ListBuffer[Field]
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def
getAddr(): BigInt
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final
def
getClass(): Class[_]
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def
getDoc(): String
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def
getFields(): List[Field]
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def
getName(): String
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def
getSize(): BigInt
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def
getfieldPtr: Int
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def
hashCode(): Int
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def
haveWO: Boolean
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val
hitDoRead: Bool
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val
hitDoWrite: Bool
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final
def
isInstanceOf[T0]: Boolean
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val
name: String
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final
def
ne(arg0: AnyRef): Boolean
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final
def
notify(): Unit
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final
def
notifyAll(): Unit
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def
rdSecurePassage(rdbits: Bits): Bits
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def
rdSecurePassage(access: Bool): Bool
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def
rdata(): Bits
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def
readBits(): Bits
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def
readErrorTag: Boolean
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def
readValid(): Bool
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val
regType: String
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lazy val
secureLogic: (Option[Bool], Option[Bool])
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val
size: BigInt
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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def
toString(): String
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var
updateReadBits: Bits
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
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final
def
wait(): Unit
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def
wrSecurePassage(wrbits: Bits): Bits
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def
wrSecurePassage(access: Bool): Bool
Deprecated Value Members
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def
finalize(): Unit
Inherited from AnyRef
Inherited from Any