MemReadWritePort

final def !=(arg0: Any): Boolean

def ##(right: Data): Bits

final def ##(): Int

def #*(count: Int): Bits

final def ==(arg0: Any): Boolean

def IFparent: Data

var _spinalTags: LinkedHashSet[SpinalTag]

def addAttribute(attribute: Attribute): MemReadWritePort.this.type

def addAttribute(name: String, value: Int): MemReadWritePort.this.type

def addAttribute(name: String, value: String): MemReadWritePort.this.type

def addAttribute(name: String): MemReadWritePort.this.type

def addTag[T <: SpinalTag](spinalTag: T): MemReadWritePort.this.type

def addTags(h: SpinalTag, tail: SpinalTag*): MemReadWritePort.this.type

def addTags[T <: SpinalTag](tags: Iterable[T]): MemReadWritePort.this.type

val address: UInt

val addressWidth: Int

def allowDirectionLessIo(): MemReadWritePort.this.type

def allowOverride(): MemReadWritePort.this.type

def allowPartialyAssigned(): MemReadWritePort.this.type

def allowPruning(): MemReadWritePort.this.type

def allowSimplifyIt(): MemReadWritePort.this.type

def allowUnsetRegToAvoidLatch(): MemReadWritePort.this.type

def as[T <: Data](dataType: HardType[T]): T

def asBits: Bits

def asData: Data

def asInOut(): MemReadWritePort.this.type

def asInput(): MemReadWritePort.this.type

final def asInstanceOf[T0]: T0

def asOutput(): MemReadWritePort.this.type

def assignAllByName(that: Bundle): Unit

def assignDontCare(): MemReadWritePort.this.type

def assignDontCareToUnasigned(): MemReadWritePort.this.type

def assignFormalRandom(kind: RandomExpKind): Unit

final def assignFrom(that: AnyRef, target: AnyRef)(implicit loc: Location): Unit

def assignFromBits(bits: Bits, hi: Int, lo: Int): Unit

def assignFromBits(bits: Bits): Unit

def assignFromBits(bits: Bits, offset: Int, bitCount: BitCount): Unit

def assignFromImpl(that: AnyRef, target: AnyRef, kind: AnyRef)(implicit loc: Location): Unit

def assignSomeByName(that: Bundle): Unit

def assignUnassignedByName(that: MultiData): Unit

def bundleAssign(that: Bundle)(f: (Data, Data) ⇒ Unit): Unit

def checkDir(that: Bundle): Boolean

def clearAll(): MemReadWritePort.this.type

def clone(): Bundle

def component: Component

final def compositAssignFrom(that: AnyRef, target: AnyRef, kind: AnyRef)(implicit loc: Location): Unit

var compositeAssign: Assignable

def copyDirectionOfImpl(that: Data): MemReadWritePort.this.type

val dataType: T

def dirString(): String

def dontSimplifyIt(): MemReadWritePort.this.type

def elements: ArrayBuffer[(String, Data)]

var elementsCache: ArrayBuffer[(String, Data)]

def elementsString: String

val enable: Bool

final def eq(arg0: AnyRef): Boolean

def equals(obj: Any): Boolean

def existsTag(cond: (SpinalTag) ⇒ Boolean): Boolean

def filterTag(cond: (SpinalTag) ⇒ Boolean): Iterable[SpinalTag]

def find(name: String): Data

def findTag(cond: (SpinalTag) ⇒ Boolean): Option[SpinalTag]

def flatten: Seq[BaseType]

def flattenForeach(body: (BaseType) ⇒ Unit): Unit

def flattenLocalName: Seq[String]

def flip(): MemReadWritePort.this.type

def foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit

def foreachTag(body: (SpinalTag) ⇒ Unit): Unit

def freeze(): MemReadWritePort.this.type

def getAheadValue(): MemReadWritePort.this.type

def getBitsWidth: Int

final def getClass(): Class[_]

def getComponent(): Component

def getComponents(): Seq[Component]

def getDirection: IODirection

def getDisplayName(): String

def getInstanceCounter: Int

def getMode: Byte

def getMuxType[T <: Data](list: TraversableOnce[T]): HardType[T]

def getName(default: String): String

def getName(): String

def getPartialName(): String

def getPath(from: Component, to: Component): Seq[Component]

def getRealSource: Any

def getRealSourceNoRec: Any

def getRefOwnersChain(): List[Any]

def getRootParent: Data

def getRtlPath(separator: String): String

def getScalaLocationLong: String

def getScalaLocationShort: String

def getScalaTrace(): Throwable

def getTag[T <: SpinalTag](clazz: Class[T]): Option[T]

def getTags(): LinkedHashSet[SpinalTag]

def getTypeString: String

def getZero: MemReadWritePort.this.type

var globalData: GlobalData

var hardtype: HardType[_]

def hasTag[T <: SpinalTag](clazz: Class[T]): Boolean

def hasTag(spinalTag: SpinalTag): Boolean

def hashCode(): Int

final def initFrom(that: AnyRef, target: AnyRef): Unit

def instanceAttributes(language: Language): Iterable[Attribute]

def instanceAttributes: Iterable[Attribute]

final def intoMaster(): MemReadWritePort.this.type

Convert into master

final def intoSlave(): MemReadWritePort.this.type

Convert into slave

def isAnalog: Boolean

def isComb: Boolean

def isCompletelyUnnamed: Boolean

def isDirectionLess: Boolean

def isEmptyOfTag: Boolean

def isInOut: Boolean

def isInput: Boolean

def isInputOrInOut: Boolean

final def isInstanceOf[T0]: Boolean

final def isMasterInterface: Boolean

Are port directions set for a Master interface?

final def isNamed: Boolean

def isOutput: Boolean

def isOutputOrInOut: Boolean

def isPriorityApplicable(namePriority: Byte): Boolean

def isReg: Boolean

def isRegOnAssign: Boolean

final def isSlaveInterface: Boolean

Are port directions set for a Master interface?

def isUnnamed: Boolean

val mask: Bits

val maskWidth: Int

var name: String

var nameableRef: Nameable

final def ne(arg0: AnyRef): Boolean

def noBackendCombMerge(): MemReadWritePort.this.type

def noCombLoopCheck(): MemReadWritePort.this.type

final def notify(): Unit

final def notifyAll(): Unit

def onEachAttributes(doIt: (Attribute) ⇒ Unit): Unit

def overrideLocalName(name: String): MemReadWritePort.this.type

var parent: Data

var parentScope: ScopeStatement

def pull(propagateName: Boolean): MemReadWritePort.this.type

def pull(): MemReadWritePort.this.type

def purify(): MemReadWritePort.this.type

def randBoot(u: Unit): MemReadWritePort.this.type

val rdata: T

var refOwner: RefOwnerType

def reflectNames(): Unit

def removeAssignments(data: Boolean, init: Boolean, initial: Boolean): MemReadWritePort.this.type

def removeDataAssignments(): MemReadWritePort.this.type

def removeInitAssignments(): MemReadWritePort.this.type

def removeTag(spinalTag: SpinalTag): MemReadWritePort.this.type

def removeTags(tags: Iterable[SpinalTag]): MemReadWritePort.this.type

def resized: MemReadWritePort.this.type

def rootIF(): Interface

def rootIFList(): List[Interface]

def rootIFrec(now: Data, lastRoot: List[Interface]): List[Interface]

var scalaTrace: Throwable

def setAll(): MemReadWritePort.this.type

def setAsAnalog(): MemReadWritePort.this.type

def setAsComb(): MemReadWritePort.this.type

def setAsDirectionLess(): MemReadWritePort.this.type

final def setAsMaster(): Unit

Set as master interface

def setAsReg(): MemReadWritePort.this.type

final def setAsSlave(): Unit

Set a slave interface

def setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): MemReadWritePort.this.type

def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): MemReadWritePort.this.type

def setCompositeName(nameable: Nameable, postfix: String): MemReadWritePort.this.type

def setCompositeName(nameable: Nameable, namePriority: Byte): MemReadWritePort.this.type

def setCompositeName(nameable: Nameable, weak: Boolean): MemReadWritePort.this.type

def setCompositeName(nameable: Nameable): MemReadWritePort.this.type

def setLambdaName(isNameBody: ⇒ Boolean)(nameGen: ⇒ String): MemReadWritePort.this.type

def setName(name: String, namePriority: Byte): MemReadWritePort.this.type

def setName(name: String, weak: Boolean): MemReadWritePort.this.type

def setName(name: String): MemReadWritePort.this.type

def setNameAsWeak(): MemReadWritePort.this.type

def setOutputAsReg(): MemReadWritePort.this.type

def setPartialName(name: String, namePriority: Byte, owner: Any): MemReadWritePort.this.type

def setPartialName(name: String, namePriority: Byte): MemReadWritePort.this.type

def setPartialName(name: String, weak: Boolean): MemReadWritePort.this.type

def setPartialName(owner: Nameable, name: String, namePriority: Byte): MemReadWritePort.this.type

def setPartialName(owner: Nameable, name: String, weak: Boolean): MemReadWritePort.this.type

def setPartialName(name: String): MemReadWritePort.this.type

def setPartialName(owner: Nameable, name: String): MemReadWritePort.this.type

def setPartialName(owner: Nameable): MemReadWritePort.this.type

def setRefOwner(that: Any): Unit

def setScalaLocated(source: ScalaLocated): MemReadWritePort.this.type

def setWeakName(name: String): MemReadWritePort.this.type

def spinalTags: LinkedHashSet[SpinalTag]

final def synchronized[T0](arg0: ⇒ T0): T0

def toIo(): MemReadWritePort.this.type

def toMuxInput[T <: Data](muxOutput: T): T

def toString(): String

def unfreeze(): MemReadWritePort.this.type

def unsetName(): MemReadWritePort.this.type

def useMask: Boolean

def valCallback[T](ref: T, name: String): T

def valCallbackOn(ref: Any, name: String, refs: Set[Any]): Unit

def valCallbackRec(ref: Any, name: String): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

final def wait(): Unit

val wdata: T

def wrapNext(): MemReadWritePort.this.type

val write: Bool

def zipByName(that: MultiData, rec: ArrayBuffer[(BaseType, BaseType)]): ArrayBuffer[(BaseType, BaseType)]

def asDirectionLess(): MemReadWritePort.this.type

def asMaster(): Unit

Override it to define port directions for a master interface.

def asSlave(): Unit

Override it to define port directions for a master interface.

def finalize(): Unit

def genIf(cond: Boolean): MemReadWritePort.this.type