R

MWR

RAS

CoreConfig SdramTiming SoftConfig

RASn

SdramInterface InitCmd SdramXdrIo SdramXdrPhyCtrlPhase Ecp5Sdrx2Phy

RCD

CoreConfig SdramTiming SoftConfig

RDY

IDELAYCTRL

READ

Axi4ToBRAMPhase Opcode I2cSlaveCmdMode SdramCtrlBackendTask FrontendCmdOutputKind

REF

CoreConfig SdramTiming SoftConfig

REFCLK

IDELAYCTRL

REFCLK_FREQUENCY

IDELAYE2 ODELAYE2

REFERENCECLK

SB_PLL40_CORE

REFRESH

SdramCtrlBackendTask FrontendCmdOutputKind

REGRST

IDELAYE2 ODELAYE2

RESERVED

burst Response

RESET

JtagState

RESETB

SB_PLL40_CORE SB_PLL40_PAD

RESETn

SdramGeneration SdramXdrIo SdramXdrPhyCtrlPhase SoftBus

RESPONSE

Phase Axi4ToApb3BridgePhase Axi4ToBRAMPhase

RESTART

I2cSlaveCmdMode

RFC

CoreConfig SdramTiming SoftConfig Tasker

ROUND_ROBIN

BmbInterconnectGenerator

RP

CoreConfig SdramTiming SoftConfig Tasker

RRD

CoreConfig SdramTiming SoftConfig Tasker

RS

OP0 OP1

RST

IDDRX1F ODDRX1F TSFF IDELAYCTRL ISERDESE2 OSERDESE2

RTP

CoreConfig SdramTiming SoftConfig

RTW

CoreConfig SoftConfig Tasker

RTY

Wishbone

RUN

SdramCtrlFrontendState

Ras_n

mt48lc16m16a2_model

ReadMapping

SpiXdrMasterCtrl

ReadRetLinked

lib

ReadableOpenDrain

io

RecFloating

math

RecFloating128

math

RecFloating16

math

RecFloating32

math

RecFloating64

math

Refresher

xdr

RegFileReadKind

impl

RegFlow

lib

Report

bench

Request

PlicTarget

ResetCtrl

lib

ResetEmitterEmitter

altera

ResetEmitterTag

altera

Response

AvalonMM

Reverse

lib

Rgb

graphic

RgbConfig

graphic

RiscvAhbLite3

build

RiscvAvalon

build

RiscvAxi4

build

RiscvCore

impl

RiscvCoreConfig

impl

Rsp

Apb3CC Bmb SpiXdrMasterCtrl

RspContext

Axi4ReadOnlyUpsizer

Rtl

bench

RtlPhy

phy

RtlPhyInterface

phy

RtlPhyWriteCmd

phy

r

Axi4 Axi4ReadOnly Axi4Shared AxiLite4 AxiLite4ReadOnly Rgb

rBeats

Axi4ReadOnlyChecker Axi4SharedChecker

rFifoSize

Axi4CC Axi4ReadyOnlyCC Axi4SharedCC

rMonitor

Axi4ReadOnlyMonitor

rPendings

Axi4ReadOnlyChecker Axi4SharedChecker

rQueue

Axi4ReadOnlyMasterAgent Axi4ReadOnlyMonitor Axi4ReadOnlySlaveAgent

rShift

ISERDESE2

rUserWidth

Axi4Config

rWidth

RgbConfig

ram

StreamFifoCC StreamFifoLowLatency AhbLite3OnChipRam AhbLite3OnChipRamMultiPort AhbLite3OnChipRom Axi4SharedOnChipRam Axi4SharedOnChipRamMultiPort BmbOnChipRam BmbOnChipRamMultiPort RtlPhy

randomAddressInRange

AddressRange

randomAdressInRange

WishboneTransaction

randomizeAddress

WishboneTransaction

randomizeData

WishboneTransaction

randomizeTGA

WishboneTransaction

randomizeTGC

WishboneTransaction

randomizeTGD

WishboneTransaction

range

BmbMasterParameterIdMapping

ras_n

mt41k128m16jt_model

rate

XdrOutput XdrPin

ratio

Axi4ReadOnlyUpsizer BmbDownSizerBridge BmbUpSizerBridge

raw

FixData

rddata

BRAM

read

TraversableOncePimped Apb3Driver AvalonMM BusSlaveFactory OpenDrainSoftConnection JtagTapAccess SpiMasterCtrlCmdData Cmd XdrPin UartCtrlIo ReadableOpenDrain TriState TriStateArray Bank CoreTask RtlPhy

readAddress

AhbLite3SlaveFactory Apb3SlaveFactory AxiLite4SlaveFactory AvalonMMSlaveFactory BRAMSlaveFactory BusSlaveFactory BusSlaveFactoryAddressWrapper AsyncMemoryBusFactory PipelinedMemoryBusSlaveFactory WishboneSlaveFactory

readAndClearOnSet

BusSlaveFactory

readAndSetOnSet

BusSlaveFactory

readAndWrite

BusSlaveFactory

readAndWriteMultiWord

BusSlaveFactory

readAtCmd

AvalonMMSlaveFactory PipelinedMemoryBusSlaveFactory

readAtRsp

AvalonMMSlaveFactory PipelinedMemoryBusSlaveFactory

readBufferLength

Parameter

readCmd

Axi4 Axi4ReadOnly AxiLite4 AxiLite4ReadOnly

readCounter

RtlPhy

readCtrl

RtlPhy

readData

Axi4SharedToBram AvalonMM AsyncMemoryBus

readDataStage

AxiLite4SlaveFactory

readDataValid

AvalonMM

readDecodings

Axi4SharedDecoder

readDelay

PhyLayout

readEnable

SdramXdrPhyCtrl

readHalt

AhbLite3SlaveFactory Apb3SlaveFactory AxiLite4SlaveFactory AvalonMMSlaveFactory BRAMSlaveFactory BusSlaveFactory BusSlaveFactoryAddressWrapper AsyncMemoryBusFactory PipelinedMemoryBusSlaveFactory WishboneSlaveFactory

readHaltRequest

AxiLite4SlaveFactory

readHexFile

HexTools

readIdPathRange

Axi4SharedArbiter

readInputConfig

Axi4SharedArbiter

readInputsCount

Axi4SharedArbiter

readLatencies

CoreParameter

readLatency

AvalonMMConfig CoreConfig

readMapping

Mod

readMultiWord

BusSlaveFactory

readOccur

AxiLite4SlaveFactory

readOnly

Axi4Upsizer

readOnlyBridger

Axi4CrossbarFactory

readPendingQueueSize

Axi4Upsizer

readPrimitive

BusSlaveFactory BusSlaveFactoryAddressWrapper BusSlaveFactoryDelayed

readRange

Axi4SharedArbiter Axi4SharedDecoder

readRsp

Axi4 Axi4ReadOnly Axi4Shared AxiLite4 AxiLite4ReadOnly AxiLite4SlaveFactory

readRspIndex

Axi4ReadOnlyArbiter Axi4ReadOnlyDecoder Axi4SharedArbiter Axi4SharedDecoder

readRspInputs

Axi4SharedArbiter

readRspSels

Axi4ReadOnlyArbiter Axi4SharedArbiter

readShifter

SdramModel

readStreamNonBlocking

BusSlaveFactory

readSyncMemWordAligned

BusSlaveFactory

readSyncPort

MemPimped

readTrigger

RtlPhy

readType

ReadRetLinked

readValid

SdramXdrPhyCtrl

readWaitTime

AvalonMMConfig

readed

RtlPhy

readedData

AhbLite3ToApb3Bridge Axi4SharedToApb3Bridge

ready

Stream AsyncMemoryBus

reduceBalancedTree

TraversableOnceAnyPimped TraversableOncePimped

ref

ScoreboardInOrder

refWidth

CoreParameter

reflectiveCalls

core

refresh

SdramCtrl CoreTasks

refresher

Core

reg

EventEmitter

regFile

RiscvCore

regFileAddress

CoreExecute1Output

regFileReadyKind

RiscvCoreConfig

region

Axi4Ax Axi4AxUnburstified

regionAllocate

BmbMasterAgent

regionFree

BmbMasterAgent

regionIsMapped

BmbMasterAgent

regs

SdrInferedPhy

release

Lock Phase

remainder

MixedDividerRsp SignedDividerRsp UnsignedDivider UnsignedDividerRsp

remainderMinusDenominator

UnsignedDivider

remainderShifted

UnsignedDivider

remaining

Axi4ReadOnlyErrorSlave Axi4SharedErrorSlave

remainingZero

Axi4ReadOnlyErrorSlave Axi4SharedErrorSlave

remapAddress

AhbLite3

remoteCmdWidth

SystemDebuggerConfig

removeOffset

AddressMapping DefaultMapping MaskMapping SingleMapping SizeMapping

repeat

Stream

report

core SdramModel

requestIndex

AhbLite3Decoder

requests

WishboneArbiter PlicTarget

requireBuffer

BmbUnburstify

requireDownSizer

SlaveModel

requireUnburstify

SlaveModel

requireUpSizer

SlaveModel

requirements

MasterModel SlaveModel

requirementsGenerator

SlaveModel

resendTimeout

SerialLinkTx

resetCtrl

Pinsec

resetCtrlClockDomain

Pinsec

resetOut

DebugExtensionIo

resolution

QFormat

resp

Axi4 Axi4B Axi4R AxiLite4 AxiLite4B AxiLite4R

response

AvalonMM

result

CoreExecute0Output CoreExecute1Output TopLevel

retain

Lock Phase

retainFor

Phase

retainer

Phase

retains

Lock

rfen

InstructionCtrl

rgbConfig

Axi4VgaCtrlGenerics Vga VgaCtrl

riscv

cpu

risingOccupancy

StreamFifoLowLatency

rootGenerators

GeneratorCompiler

roundRobin

OHMasking Arbitration StreamArbiterFactory WishboneArbiter

roundRobinArbiter

AhbLite3Arbiter AhbLite3CrossbarFactory

roundType

FixData

routeBuffer

Axi4WriteOnlyArbiter

routeBufferLatency

Axi4SharedArbiter Axi4WriteOnlyArbiter

routeBufferM2sPipe

Axi4SharedArbiter

routeBufferS2mPipe

Axi4SharedArbiter Axi4WriteOnlyArbiter

routeBufferSize

Axi4SharedArbiter Axi4WriteOnlyArbiter

routeDataInput

Axi4WriteOnlyArbiter

row

SdramCtrlBank SdramAddress Address

rowColumn

SdramCtrlBackendCmd

rowSize

SdramLayout

rowWidth

SdramLayout

rsp

rspArea

BmbDownSizerBridge BmbUpSizerBridge Block VideoDma

rspBankSel

BmbIce40Spram

rspBit

SpiSlaveCtrl

rspBitSampled

SpiSlaveCtrl

rspBuffer

BmbAdapter

rspBufferSize

BmbPortParameter

rspContext

BmbToCorePort

rspCounter

Axi4ReadOnlyMasterAgent Axi4WriteOnlyMasterAgent

rspFifoDepth

SpiMasterCtrlMemoryMappedConfig MemoryMappingParameters

rspLogic

Axi4WriteOnlyUpsizer BmbLengthFixer

rspMonitor

Axi4ReadOnlyMasterAgent Axi4WriteOnlyMasterAgent BmbMasterAgent

rspPipe

PipelinedMemoryBus

rspPipeline

Backend

rspPop

Backend

rspQueue

BmbMasterAgent

rspRouteQueue

PipelinedMemoryBusArbiter

rspdM2sPipe

Bmb

rspdS2mPipe

Bmb

rst_n

mt41k128m16jt_model

run

Axi4VgaCtrl

rwn

AsyncMemoryBus

rx

SpiSlaveCtrlIo UartCtrl

rxFifoDepth

SpiSlaveCtrlMemoryMappedConfig UartCtrlMemoryMappedConfig

rxPtr

SerialLinkRx SerialLinkRxToTx

rxSamplePerBit

UartCtrlGenerics

rxd

Uart