Stream

final def !=(arg0: Any): Boolean

def ##(right: Data): Bits

final def ##(): Int

def #*(count: Int): Bits

def &(cond: Bool): Stream[T]

def <-/<(that: Stream[T]): Stream[T]

Connect that to this.

def <-<(that: Stream[T]): Stream[T]

Connect that to this.

def </<(that: Stream[T]): Stream[T]

Connect that to this.

def <<(that: Stream[T]): Stream[T]

Connect that to this

final def ==(arg0: Any): Boolean

def >->(into: Stream[T]): Stream[T]

Connect this to that.

def >/->(into: Stream[T]): Stream[T]

Connect that to this.

def >/>(that: Stream[T]): Stream[T]

Connect this to that.

def >>(into: Stream[T]): Stream[T]

Connect this to that

var _spinalTags: LinkedHashSet[SpinalTag]

def addAttribute(attribute: Attribute): Stream.this.type

def addAttribute(name: String, value: Int): Stream.this.type

def addAttribute(name: String, value: String): Stream.this.type

def addAttribute(name: String): Stream.this.type

def addFragmentLast(counter: Counter): Stream[Fragment[T]]

Like addFragmentLast(Bool), but instead of manually telling which values go together, let a counter do the job.

def addFragmentLast(last: Bool): Stream[Fragment[T]]

Convert this stream to a fragmented stream by adding a last bit.

def addTag[T <: SpinalTag](spinalTag: T): Stream.this.type

def addTags[T <: SpinalTag](tags: Iterable[T]): Stream.this.type

def allowDirectionLessIo(): Stream.this.type

def allowOverride(): Stream.this.type

def allowPartialyAssigned(): Stream.this.type

def allowPruning(): Stream.this.type

def allowSimplifyIt(): Stream.this.type

def allowUnsetRegToAvoidLatch(): Stream.this.type

def arbitrationFrom[T2 <: Data](that: Stream[T2]): Unit

Drive arbitration signals of this from that

def as[T <: Data](dataType: HardType[T]): T

def asBits: Bits

def asData: Data

def asDataStream: Stream[Data]

def asFlow: Flow[T]

def asInOut(): Stream.this.type

def asInput(): Stream.this.type

final def asInstanceOf[T0]: T0

def asOutput(): Stream.this.type

def assignAllByName(that: Bundle): Unit

def assignDontCare(): Stream.this.type

def assignFormalRandom(kind: RandomExpKind): Unit

final def assignFrom(that: AnyRef, target: AnyRef)(implicit loc: Location): Unit

def assignFromBits(bits: Bits, hi: Int, lo: Int): Unit

def assignFromBits(bits: Bits): Unit

def assignFromBits(bits: Bits, offset: Int, bitCount: BitCount): Unit

def assignSomeByName(that: Bundle): Unit

def assignUnassignedByName(that: MultiData): Unit

def bundleAssign(that: Bundle)(f: (Data, Data) ⇒ Unit): Unit

def ccToggle(pushClock: ClockDomain, popClock: ClockDomain): Stream[T]

def ccToggleWithoutBuffer(pushClock: ClockDomain, popClock: ClockDomain): Stream[T]

def clearValidWhen(cond: Bool): Stream[T]

def clone(): Stream[T]

def combStage(): Stream[T]

A combinatorial stage doesn't do anything, but it is nice to separate signals for combinatorial transformations.

def component: Component

final def compositAssignFrom(that: AnyRef, target: AnyRef, kind: AnyRef)(implicit loc: Location): Unit

var compositeAssign: Assignable

def connectFrom(that: Stream[T]): Stream[T]

def continueWhen(cond: Bool): Stream[T]

Block this when cond is False.

def copyDirectionOfImpl(that: Data): Stream.this.type

def dirString(): String

def dontSimplifyIt(): Stream.this.type

def elements: ArrayBuffer[(String, Data)]

var elementsCache: ArrayBuffer[(String, Data)]

def elementsString: String

final def eq(arg0: AnyRef): Boolean

def equals(obj: Any): Boolean

def existsTag(cond: (SpinalTag) ⇒ Boolean): Boolean

def filterTag(cond: (SpinalTag) ⇒ Boolean): Iterable[SpinalTag]

def find(name: String): Data

def findTag(cond: (SpinalTag) ⇒ Boolean): Option[SpinalTag]

def fire: Bool

Return True when a transaction occurs on the bus (valid && ready)

def flatten: Seq[BaseType]

def flattenForeach(body: (BaseType) ⇒ Unit): Unit

def flattenLocalName: Seq[String]

def flip(): Stream.this.type

def foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit

def foreachTag(body: (SpinalTag) ⇒ Unit): Unit

def forkSerial(cond: Bool): Stream[T]

def formalAssertsMaster(payloadInvariance: Boolean = true)(implicit loc: Location): Composite[Stream[T]] { val stack: String }

Assert that this stream conforms to the stream semantics: https://spinalhdl.github.io/SpinalDoc-RTD/dev/SpinalHDL/Libraries/stream.html#semantics - After being asserted, valid may only be deasserted once the current payload was acknowleged.

def formalAssertsOrder(dataAhead: T, dataBehind: T)(implicit loc: Location): (Bool, Bool)

def formalAssertsTimeout(maxStallCycles: Int = 0): Composite[Stream[T]] { val logic: spinal.core.Area{val counter: spinal.lib.Counter} }

Assert that this stream conforms to the stream semantics: https://spinalhdl.github.io/SpinalDoc-RTD/dev/SpinalHDL/Libraries/stream.html#semantics - After being asserted, valid should be acknowledged in limited cycles.

def formalAssumesOrder(dataAhead: T, dataBehind: T)(implicit loc: Location): (Bool, Bool)

def formalAssumesSlave(payloadInvariance: Boolean = true)(implicit loc: Location): Composite[Stream[T]]

def formalAssumesTimeout(maxStallCycles: Int = 0): Composite[Stream[T]] { val logic: spinal.core.Area{val counter: spinal.lib.Counter} }

def formalCovers(back2BackCycles: Int = 1): Composite[Stream[T]] { val hist: spinal.core.Bool }

def fragmentTransaction(bitsWidth: Int): Stream[Fragment[Bits]]

def freeRun(): Stream.this.type

def freeze(): Stream.this.type

def genIf(cond: Boolean): Stream.this.type

def getAheadValue(): Stream.this.type

def getBitsWidth: Int

final def getClass(): Class[_]

def getComponent(): Component

def getComponents(): Seq[Component]

def getDirection: IODirection

def getDisplayName(): String

def getInstanceCounter: Int

def getMode: Byte

def getMuxType[T <: Data](list: TraversableOnce[T]): HardType[T]

def getName(default: String): String

def getName(): String

def getPartialName(): String

def getPath(from: Component, to: Component): Seq[Component]

def getRealSource: Any

def getRealSourceNoRec: Any

def getRefOwnersChain(): List[Any]

def getRootParent: Data

def getRtlPath(separator: String): String

def getScalaLocationLong: String

def getScalaLocationShort: String

def getScalaTrace(): Throwable

def getTag[T <: SpinalTag](clazz: Class[T]): Option[T]

def getTags(): LinkedHashSet[SpinalTag]

def getTypeString: String

def getZero: Stream.this.type

val globalData: GlobalData

def halfPipe(flush: Bool = null): Stream[T]

cut all path, but divide the bandwidth by 2, 1 cycle latency

def haltWhen(cond: Bool): Stream[T]

Stop transactions on this when cond is True.

var hardtype: HardType[_]

def hasTag[T <: SpinalTag](clazz: Class[T]): Boolean

def hasTag(spinalTag: SpinalTag): Boolean

def hashCode(): Int

final def initFrom(that: AnyRef, target: AnyRef): Unit

def instanceAttributes(language: Language): Iterable[Attribute]

def instanceAttributes: Iterable[Attribute]

final def intoMaster(): Stream.this.type

Convert into master

final def intoSlave(): Stream.this.type

Convert into slave

def isAnalog: Boolean

def isComb: Boolean

def isCompletelyUnnamed: Boolean

def isDirectionLess: Boolean

def isEmptyOfTag: Boolean

def isFree: Bool

Return True when the bus is ready, but no data is present

def isInOut: Boolean

def isInput: Boolean

def isInputOrInOut: Boolean

final def isInstanceOf[T0]: Boolean

final def isMasterInterface: Boolean

Are port directions set for a Master interface?

def isNamed: Boolean

def isNew: Bool

Return True when a transaction has appeared (first cycle)

def isOutput: Boolean

def isOutputOrInOut: Boolean

def isPriorityApplicable(namePriority: Byte): Boolean

def isReg: Boolean

def isRegOnAssign: Boolean

final def isSlaveInterface: Boolean

Are port directions set for a Master interface?

def isStall: Bool

Return True when a transaction is present on the bus but the ready signal is low

def isUnnamed: Boolean

def m2sPipe(collapsBubble: Boolean = true, crossClockData: Boolean = false, flush: Bool = null, holdPayload: Boolean = false): Stream[T]

def map[T2 <: Data](translate: (T) ⇒ T2): Stream[T2]

var name: String

var nameableRef: Nameable

final def ne(arg0: AnyRef): Boolean

def noBackendCombMerge(): Stream.this.type

def noCombLoopCheck(): Stream.this.type

final def notify(): Unit

final def notifyAll(): Unit

def onEachAttributes(doIt: (Attribute) ⇒ Unit): Unit

def overrideLocalName(name: String): Stream.this.type

var parent: Data

var parentScope: ScopeStatement

val payload: T

val payloadType: HardType[T]

def pipelined(m2s: Boolean = false, s2m: Boolean = false, halfRate: Boolean = false): Stream[T]

def pipelined(pipe: StreamPipe): Stream[T]

def pull(propagateName: Boolean): Stream.this.type

def pull(): Stream.this.type

def purify(): Stream.this.type

def queue(size: Int, pushClock: ClockDomain, popClock: ClockDomain): Stream[T]

Connect this to an clock crossing fifo and return its pop stream

def queue(size: Int): Stream[T]

Connect this to a fifo and return its pop stream

def queueLowLatency(size: Int, latency: Int = 0): Stream[T]

Connect this to a zero latency fifo and return its pop stream

def queueWithAvailability(size: Int): (Stream[T], UInt)

def queueWithOccupancy(size: Int): (Stream[T], UInt)

Connect this to a fifo and return its pop stream and its occupancy

def queueWithPushOccupancy(size: Int, pushClock: ClockDomain, popClock: ClockDomain): (Stream[T], UInt)

Connect this to a cross clock domain fifo and return its pop stream and its push side occupancy

def randBoot(u: Unit): Stream.this.type

val ready: Bool

var refOwner: RefOwnerType

def reflectNames(): Unit

def removeAssignments(data: Boolean, init: Boolean, initial: Boolean): Stream.this.type

def removeDataAssignments(): Stream.this.type

def removeInitAssignments(): Stream.this.type

def removeTag(spinalTag: SpinalTag): Stream.this.type

def removeTags(tags: Iterable[SpinalTag]): Stream.this.type

def repeat(times: Int): (Stream[T], UInt)

Connect this to a new stream that only advances every n elements, thus repeating the input several times.

def resized: Stream.this.type

def s2mPipe(stagesCount: Int): Stream[T]

def s2mPipe(flush: Bool = null): Stream[T]

var scalaTrace: Throwable

def setAsAnalog(): Stream.this.type

def setAsComb(): Stream.this.type

def setAsDirectionLess(): Stream.this.type

final def setAsMaster(): Unit

Set as master interface

def setAsReg(): Stream.this.type

final def setAsSlave(): Unit

Set a slave interface

def setBlocked(): Stream.this.type

def setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): Stream.this.type

def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): Stream.this.type

def setCompositeName(nameable: Nameable, postfix: String): Stream.this.type

def setCompositeName(nameable: Nameable, namePriority: Byte): Stream.this.type

def setCompositeName(nameable: Nameable, weak: Boolean): Stream.this.type

def setCompositeName(nameable: Nameable): Stream.this.type

def setIdle(): Stream.this.type

def setLambdaName(isNameBody: ⇒ Boolean)(nameGen: ⇒ String): Stream.this.type

def setName(name: String, namePriority: Byte): Stream.this.type

def setName(name: String, weak: Boolean): Stream.this.type

def setName(name: String): Stream.this.type

def setNameAsWeak(): Stream.this.type

def setPartialName(name: String, namePriority: Byte, owner: Any): Stream.this.type

def setPartialName(name: String, namePriority: Byte): Stream.this.type

def setPartialName(name: String, weak: Boolean): Stream.this.type

def setPartialName(owner: Nameable, name: String, namePriority: Byte): Stream.this.type

def setPartialName(owner: Nameable, name: String, weak: Boolean): Stream.this.type

def setPartialName(name: String): Stream.this.type

def setPartialName(owner: Nameable, name: String): Stream.this.type

def setPartialName(owner: Nameable): Stream.this.type

def setRefOwner(that: Any): Unit

def setScalaLocated(source: ScalaLocated): Stream.this.type

def setWeakName(name: String): Stream.this.type

def slowdown(factor: Int): Stream[Vec[T]]

Connect this to a new stream whose payload is n times as wide, but that only fires every n cycles.

def spinalTags: LinkedHashSet[SpinalTag]

def stage(): Stream[T]

Connect this to a valid/payload register stage and return its output stream

def swapPayload[T2 <: Data](that: HardType[T2]): Stream[T2]

final def synchronized[T0](arg0: ⇒ T0): T0

def takeWhen(cond: Bool): Stream[T]

Drop transaction of this when cond is False.

def throwWhen(cond: Bool): Stream[T]

Drop transactions of this when cond is True.

def toEvent(): Event

Ignore the payload

def toFlow: Flow[T]

def toFlowFire: Flow[T]

def toIo(): Stream.this.type

def toMuxInput[T <: Data](muxOutput: T): T

def toReg(init: T): T

def toReg(): T

def toString(): String

def translateFrom[T2 <: Data](that: Stream[T2])(dataAssignment: (T, payload.type) ⇒ Unit): Stream[T]

def translateInto[T2 <: Data](into: Stream[T2])(dataAssignment: (T2, T) ⇒ Unit): Stream[T2]

def translateWith[T2 <: Data](that: T2): Stream[T2]

Replace this stream's payload with another one

def transmuteWith[T2 <: Data](that: HardType[T2]): Stream[T2]

Change the payload's content type.

def unfreeze(): Stream.this.type

def unsetName(): Stream.this.type

def valCallback[T](ref: T, name: String): T

def valCallbackOn(ref: Any, name: String, refs: Set[Any]): Unit

def valCallbackRec(ref: Any, name: String): Unit

val valid: Bool

def validPipe(): Stream[T]

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

final def wait(): Unit

def wrapNext(): Stream.this.type

def zipByName(that: MultiData, rec: ArrayBuffer[(BaseType, BaseType)]): ArrayBuffer[(BaseType, BaseType)]

def ~[T2 <: Data](that: T2): Stream[T2]

def ~~[T2 <: Data](translate: (T) ⇒ T2): Stream[T2]

def asDirectionLess(): Stream.this.type

def asMaster(): Unit

Override it to define port directions for a master interface.

def asSlave(): Unit

Override it to define port directions for a master interface.

def finalize(): Unit