Bus word width in bytes
Handle write command, write, and write response channel as implemented by Altera/Intel on their Cyclone 5 platform.
Handle write command, write, and write response channel as implemented by Altera/Intel on their Cyclone 5 platform. Their implementation behaves as all three channels are coupled. The implementation waits until all words for a write operation have been transfered. Then it asserts the AWREADY to accept the write command. After that, BVALID is asserted.
AXI write channel
AXI write command channel
AXI write response channel
(Since version ) see corresponding Javadoc for more information.