Number of element stored in the fifo, Note that if withAsyncRead==false, then one extra transaction can be stored
Read the memory using asyncronous read port (ex distributed ram). If false, add 1 cycle latency
Bypass the push port to the pop port when the fifo is empty. If false, add 1 cycle latency Only available if withAsyncRead == true
Tune the design to get the maximal clock frequency
Use an Vec of register instead of a Mem to store the content Only available if withAsyncRead == true
Number of element stored in the fifo, Note that if withAsyncRead==false, then one extra transaction can be stored
Tune the design to get the maximal clock frequency
Use an Vec of register instead of a Mem to store the content Only available if withAsyncRead == true
Read the memory using asyncronous read port (ex distributed ram).
Read the memory using asyncronous read port (ex distributed ram). If false, add 1 cycle latency
Bypass the push port to the pop port when the fifo is empty.
Bypass the push port to the pop port when the fifo is empty. If false, add 1 cycle latency Only available if withAsyncRead == true
(Since version ) see corresponding Javadoc for more information.
Fully redesigned in release 1.8.2 allowing improved timing closure. - latency of 0, 1, 2 cycles