PipelinedMemoryBusSlaveFactory

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

var _config: BusSlaveFactoryConfig

Configuration of the BusSlaveFactory

val _context: Capture

final def asInstanceOf[T0]: T0

val askRead: Bool

val askWrite: Bool

def build(): Unit

In this function you have to define the read/write logic thanks to element, elementsPerAddress and elementsPerRangeAddress This is the only thing with def busDataWidth that should be implement by class that extends BusSlaveFactoryDelay

def busDataWidth: Int

Return the data width of the bus

def childNamePriority: Byte

def clearOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T

def clone(): AnyRef

def component: Component

def createAndDriveFlow[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): Flow[T]

Create a writable Flow register of type dataType at address and placed at bitOffset in the word

def createReadAndClearOnSet[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): T

def createReadAndSetOnSet[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): T

def createReadAndWrite[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

Create a read write register of type dataType at address and placed at bitOffset in the word

def createReadMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T

Create multi-words read register of type dataType

def createReadOnly[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

Create a read only register of type dataType at address and placed at bitOffset in the word

def createWriteAndReadMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T

Create multi-words write and read register of type dataType

def createWriteMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T

Create multi-words write register of type dataType

def createWriteOnly[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

Create a write only register of type dataType at address and placed at bitOffset in the word

def dataModelString(): String

def doBitsAccumulationAndClearOnRead(that: Bits, address: BigInt, bitOffset: Int = 0): Unit

Instantiate an internal register which at each cycle do : reg := reg | that Then when a read occur, the register is cleared.

def doMappedElements(jobs: Seq[BusSlaveFactoryElement], askWrite: Bool, askRead: Bool, doWrite: Bool, doRead: Bool, writeData: Bits, readData: Bits): Unit

def doMappedReadElements(jobs: Seq[BusSlaveFactoryElement], askRead: Bool, doRead: Bool, readData: Bits): Unit

def doMappedWriteElements(jobs: Seq[BusSlaveFactoryElement], askWrite: Bool, doWrite: Bool, writeData: Bits): Unit

def doNonStopWrite(writeData: Bits): Unit

val doRead: Bool

val doWrite: Bool

def drive[T <: Data](address: BigInt, bitMapping: (Int, Data)*): Unit

def drive[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

Drive that with a register writable at address placed at bitOffset in the word

def driveAndRead[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

Drive that with a register writable and readable at address placed at bitOffset in the word

def driveAndReadMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T

Drive and read that on multi-word

def driveFlow[T <: Data](that: Flow[T], address: BigInt, bitOffset: Int = 0): Unit

Emit on that a transaction when a write happen at address by using data placed at bitOffset in the word

def driveMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T

Drive that on multi-words

val elements: ArrayBuffer[BusSlaveFactoryElement]

Contains all elements created

val elementsOk: HashSet[BusSlaveFactoryElement]

val elementsPerAddress: LinkedHashMap[AddressMapping, ArrayBuffer[BusSlaveFactoryElement]]

Contains all elements related to an address

final def eq(arg0: AnyRef): Boolean

def equals(obj: Any): Boolean

def foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit

final def getClass(): Class[_]

def getConfig: BusSlaveFactoryConfig

def getDisplayName(): String

def getInstanceCounter: Int

def getMode: Byte

def getName(default: String): String

def getName(): String

def getPartialName(): String

def getPath(from: Component, to: Component): Seq[Component]

def getRefOwnersChain(): List[Any]

def getScalaLocationLong: String

def getScalaLocationShort: String

def getScalaTrace(): Throwable

val globalData: GlobalData

def hashCode(): Int

def isCompletelyUnnamed: Boolean

final def isInstanceOf[T0]: Boolean

def isNamed: Boolean

def isPriorityApplicable(namePriority: Byte): Boolean

def isReading(address: BigInt): Bool

Return true if the bus is reading

def isUnnamed: Boolean

def isWriting(address: BigInt): Bool

Return true if the bus is writing

def multiCycleRead(address: AddressMapping, cycles: BigInt): Unit

var name: String

var nameableRef: Nameable

final def ne(arg0: AnyRef): Boolean

def nonStopWrite[T <: Data](that: T, bitOffset: Int = 0, documentation: String = null): T

Permanently assign that by the bus write data from bitOffset

final def notify(): Unit

final def notifyAll(): Unit

def onRead(address: BigInt, documentation: String = null)(doThat: ⇒ Unit): Unit

Call doThat when a read transaction occurs on address

def onReadPrimitive(address: AddressMapping, haltSensitive: Boolean, documentation: String)(doThat: ⇒ Unit): Unit

def onWrite(address: BigInt, documentation: String = null)(doThat: ⇒ Unit): Unit

Call doThat when a write transaction occurs on address

def onWritePrimitive(address: AddressMapping, haltSensitive: Boolean, documentation: String)(doThat: ⇒ Unit): Unit

def overrideLocalName(name: String): PipelinedMemoryBusSlaveFactory.this.type

var parentScope: ScopeStatement

def printDataModel(): Unit

def read[T <: Data](address: BigInt, bitMapping: (Int, Data)*): Unit

def read[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

When the bus read the address, fill the response with that at bitOffset

def readAddress(): UInt

def readAddress(address: AddressMapping): UInt

def readAndClearOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T

def readAndSetOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T

def readAndWrite(that: Data, address: BigInt, bitOffset: Int = 0, documentation: String = null): Unit

Make that readable and writable at address and placed at bitOffset in the word

def readAndWriteMultiWord(that: Data, address: BigInt, documentation: String = null): Unit

Create the memory mapping to write/read that from address

val readAtCmd: Flow[Bits]

val readAtRsp: Flow[Bits]

def readError(): Unit

val readErrorFlag: Bool

def readFire(): Bool

def readHalt(): Unit

def readMultiWord(that: Data, address: BigInt, documentation: String = null): Unit

Create the memory mapping to read that from address If that is bigger than one word it extends the register on following addresses.

def readPrimitive[T <: Data](that: T, address: AddressMapping, bitOffset: Int, documentation: String): Unit

def readStreamNonBlocking[T <: Data](that: Stream[T], address: BigInt, validBitOffset: Int, payloadBitOffset: Int, validInverted: Boolean = false): Unit

Read that and consume the transaction when a read happen at address.

def readStreamNonBlocking[T <: Data](that: Stream[T], address: BigInt): Unit

Read that (that is bigger than the busWidth) and consume the transaction when a read happen at address.

def readSyncMemMultiWord[T <: Data](mem: Mem[T], addressOffset: BigInt): Mem[T]

Memory map a Mem to bus for reading.

def readSyncMemWordAligned[T <: Data](mem: Mem[T], addressOffset: BigInt, bitOffset: Int = 0): Mem[T]

var refOwner: RefOwnerType

def reflectNames(): Unit

def rework[T](body: ⇒ T): T

var scalaTrace: Throwable

def setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): PipelinedMemoryBusSlaveFactory.this.type

def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): PipelinedMemoryBusSlaveFactory.this.type

def setCompositeName(nameable: Nameable, postfix: String): PipelinedMemoryBusSlaveFactory.this.type

def setCompositeName(nameable: Nameable, namePriority: Byte): PipelinedMemoryBusSlaveFactory.this.type

def setCompositeName(nameable: Nameable, weak: Boolean): PipelinedMemoryBusSlaveFactory.this.type

def setCompositeName(nameable: Nameable): PipelinedMemoryBusSlaveFactory.this.type

def setConfig(value: BusSlaveFactoryConfig): PipelinedMemoryBusSlaveFactory.this.type

def setLambdaName(isNameBody: ⇒ Boolean)(nameGen: ⇒ String): PipelinedMemoryBusSlaveFactory.this.type

def setName(name: String, namePriority: Byte): PipelinedMemoryBusSlaveFactory.this.type

def setName(name: String, weak: Boolean): PipelinedMemoryBusSlaveFactory.this.type

def setName(name: String): PipelinedMemoryBusSlaveFactory.this.type

def setNameAsWeak(): PipelinedMemoryBusSlaveFactory.this.type

def setOnClear[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T

def setOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T

def setPartialName(name: String, namePriority: Byte, owner: Any): PipelinedMemoryBusSlaveFactory.this.type

def setPartialName(name: String, namePriority: Byte): PipelinedMemoryBusSlaveFactory.this.type

def setPartialName(name: String, weak: Boolean): PipelinedMemoryBusSlaveFactory.this.type

def setPartialName(owner: Nameable, name: String, namePriority: Byte): PipelinedMemoryBusSlaveFactory.this.type

def setPartialName(owner: Nameable, name: String, weak: Boolean): PipelinedMemoryBusSlaveFactory.this.type

def setPartialName(name: String): PipelinedMemoryBusSlaveFactory.this.type

def setPartialName(owner: Nameable, name: String): PipelinedMemoryBusSlaveFactory.this.type

def setPartialName(owner: Nameable): PipelinedMemoryBusSlaveFactory.this.type

def setRefOwner(that: Any): Unit

def setScalaLocated(source: ScalaLocated): PipelinedMemoryBusSlaveFactory.this.type

def setWeakName(name: String): PipelinedMemoryBusSlaveFactory.this.type

def setWordEndianness(value: Endianness): BusSlaveFactory

Set the endianness during write/read multiword

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

def unsetName(): PipelinedMemoryBusSlaveFactory.this.type

def valCallback[T](ref: T, name: String): T

def valCallbackOn(ref: Any, name: String, refs: Set[Any]): Unit

def valCallbackRec(obj: Any, name: String): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

final def wait(): Unit

def withOffset(offset: BigInt): BusSlaveFactoryAddressWrapper

def wordAddressInc: Int

Address incrementation used by the read and write multi words registers

def write[T <: Data](address: BigInt, bitMapping: (Int, Data)*): Unit

def write[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

When the bus write the address, assign that with bus’s data from bitOffset

def writeAddress(): UInt

def writeAddress(address: AddressMapping): UInt

def writeByteEnable(): Bits

Byte enable bits, defaulting to all ones

def writeError(): Unit

val writeErrorFlag: Bool

def writeFire(): Bool

def writeHalt(): Unit

def writeMemMultiWord[T <: Data](mem: Mem[T], addressOffset: BigInt): Mem[T]

Memory map a Mem to bus for writing.

def writeMemWordAligned[T <: Data](mem: Mem[T], addressOffset: BigInt, bitOffset: Int = 0): Mem[T]

def writeMultiWord(that: Data, address: BigInt, documentation: String = null): Unit

Create the memory mapping to write that at address.

def writePrimitive[T <: Data](that: T, address: AddressMapping, bitOffset: Int, documentation: String): Unit

def createReadWrite[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): T

def finalize(): Unit