class
SimVpi extends SimRaw
Instance Constructors
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new
SimVpi(backend: VpiBackend)
Value Members
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final
def
!=(arg0: Any): Boolean
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final
def
##(): Int
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final
def
==(arg0: Any): Boolean
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final
def
asInstanceOf[T0]: T0
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def
clone(): AnyRef
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def
disableWave(): Unit
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def
enableWave(): Unit
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def
end(): Unit
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final
def
eq(arg0: AnyRef): Boolean
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def
equals(arg0: Any): Boolean
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def
eval(): Boolean
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val
filledByte: Byte
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def
getBigInt(signal: Signal): BigInt
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def
getBigIntMem(signal: Signal, index: Long): BigInt
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final
def
getClass(): Class[_]
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def
getInt(signal: Signal): Int
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def
getIntMem(signal: Signal, index: Long): Int
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def
getLong(signal: Signal): Long
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def
getLongMem(signal: Signal, index: Long): Long
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def
getSignalId(signal: Signal): Long
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val
handleMap: HashMap[Int, Long]
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def
hashCode(): Int
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def
isBufferedWrite: Boolean
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final
def
isInstanceOf[T0]: Boolean
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final
def
ne(arg0: AnyRef): Boolean
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final
def
notify(): Unit
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final
def
notifyAll(): Unit
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def
randomize(seed: Long): Unit
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def
setBigInt(signal: Signal, value: BigInt): Unit
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def
setBigIntMem(signal: Signal, value: BigInt, index: Long): Unit
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def
setInt(signal: Signal, value: Int): Unit
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def
setIntMem(signal: Signal, value: Int, index: Long): Unit
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def
setLong(signal: Signal, value: Long): Unit
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def
setLongMem(signal: Signal, value: Long, index: Long): Unit
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def
sleep(cycles: Long): Unit
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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val
thread: Thread
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def
toString(): String
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var
userData: Any
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
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final
def
wait(): Unit
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val
zeroByte: Byte
Deprecated Value Members
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def
finalize(): Unit
Inherited from AnyRef
Inherited from Any