de.sciss.synth.ugen

DC

object DC extends Serializable

A UGen that creates a constant signal at a given calculation rate.

Examples
// create a silent audio signal
play {
  // Note: Select.ar requires audio-rate input.
  // Therefore, DC can be used to wrap the otherwise
  // incompatible constant zero. In future versions of
  // ScalaCollider, this wrapping will be done
  // automatically, however.
  Select.ar(MouseButton.kr(lag = 0), Seq(DC.ar(0), SinOsc.ar * 0.2))
}
See also

LeakDC

Linear Supertypes
Serializable, Serializable, AnyRef, Any
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  1. final def !=(arg0: AnyRef): Boolean

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  2. final def !=(arg0: Any): Boolean

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  3. final def ##(): Int

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  4. final def ==(arg0: AnyRef): Boolean

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  5. final def ==(arg0: Any): Boolean

    Definition Classes
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  6. def ar(in: GE): DC

    in

    constant value to output, fixed at initialisation time. (init-time only)

  7. final def asInstanceOf[T0]: T0

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  8. def clone(): AnyRef

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  9. final def eq(arg0: AnyRef): Boolean

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  10. def equals(arg0: Any): Boolean

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  11. def finalize(): Unit

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  12. final def getClass(): Class[_]

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  13. def hashCode(): Int

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  14. final def isInstanceOf[T0]: Boolean

    Definition Classes
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  15. def kr(in: GE): DC

    in

    constant value to output, fixed at initialisation time. (init-time only)

  16. final def ne(arg0: AnyRef): Boolean

    Definition Classes
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  17. final def notify(): Unit

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  18. final def notifyAll(): Unit

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  19. final def synchronized[T0](arg0: ⇒ T0): T0

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  20. def toString(): String

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  21. final def wait(): Unit

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  22. final def wait(arg0: Long, arg1: Int): Unit

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  23. final def wait(arg0: Long): Unit

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