Spec base class for BDD-style testers.
Spec base class for property-based testers.
Common utility functions for Chisel unit tests.
experimental version of a Tester that allows arbitrary testing circuitry to be run in some order
provide common facilities for step based testing and decoupled interface testing
named access and type information about the IO bundle of a module used for building testing harnesses
Base class supports implementation of test circuits of modules that use Decoupled inputs and either Decoupled or Valid outputs Multiple decoupled inputs are supported.
Base class supports implementation of test circuits of modules that use Decoupled inputs and either Decoupled or Valid outputs Multiple decoupled inputs are supported. Testers that subclass this will be strictly ordered. Input will flow into their devices asynchronously but in order they were generated be compared in the order they are generated
class XTimesXTester extends [[OrderedDecoupledHWIOTester]] { val device_under_test = new XTimesY test_block { for { i <- 0 to 10 j <- 0 to 10 } { input_event(device_under_test.io.in.x -> i, device_under_test.in.y -> j) output_event(device_under_test.io.out.z -> i*j) } } }
an input event is a series of values that will be gated into the decoupled input interface at the same time an output event is a series of values that will be tested at the same time independent small state machines are set up for input and output interface all inputs regardless of interfaces are submitted to the device under test in the order in which they were created likewise, all outputs regardless of which interface are tested in the same order that they were created
Use a UnitTester to construct a test harness for a chisel module this module will be canonically referred to as the device_under_test, often simply as c in a unit test, and also dut The UnitTester is used to put series of values (as chisel3.Vec's) into the ports of the dut io which are INPUT At specified times it check the dut io OUTPUT ports to see that they match a specific value The vec's are assembled through the following API poke, expect and step, pokes
Use a UnitTester to construct a test harness for a chisel module this module will be canonically referred to as the device_under_test, often simply as c in a unit test, and also dut The UnitTester is used to put series of values (as chisel3.Vec's) into the ports of the dut io which are INPUT At specified times it check the dut io OUTPUT ports to see that they match a specific value The vec's are assembled through the following API poke, expect and step, pokes
class Adder(width:Int) extends Module { val io = new Bundle { val in0 : UInt(INPUT, width=width) val in1 : UInt(INPUT, width=width) val out : UInt(OUTPUT, width=width) } } class AdderTester extends UnitTester { val device_under_test = Module( new Adder(32) ) testBlock { poke(c.io.in0, 5) poke(c.io.in1, 7) expect(c.io.out, 12) } }
Generates the Module specific verilator harness cpp file for verilator compilation
Copies the necessary header files used for verilator compilation to the specified destination folder
Copies the necessary header files used for verilator compilation to the specified destination folder
Generates the Module specific verilator harness cpp file for verilator compilation