Chisel

Type Members

type Aggregate = chisel3.Aggregate
type Arbiter[T <: Data] = chisel3.util.Arbiter[T]
type ArbiterIO[T <: Data] = chisel3.util.ArbiterIO[T]
type BackendCompilationUtilities = firrtl.util.BackendCompilationUtilities
type BitPat = chisel3.util.BitPat
type Bits = chisel3.Bits
type Bool = chisel3.Bool
type Bundle = chisel3.Bundle
type ChiselException = chisel3.internal.ChiselException
type Clock = chisel3.Clock
type Counter = chisel3.util.Counter
type Data = chisel3.Data
type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T]
type Element = chisel3.Element
type LockingArbiter[T <: Data] = chisel3.util.LockingArbiter[T]
type LockingArbiterLike[T <: Data] = chisel3.util.LockingArbiterLike[T]
type LockingRRArbiter[T <: Data] = chisel3.util.LockingRRArbiter[T]
type Mem[T <: Data] = chisel3.Mem[T]
type MemBase[T <: Data] = chisel3.MemBase[T]
type Module = CompatibilityModule
type Num[T <: Data] = chisel3.Num[T]
type Pipe[T <: Data] = chisel3.util.Pipe[T]
type Queue[T <: Data] = QueueCompatibility[T]
type QueueIO[T <: Data] = chisel3.util.QueueIO[T]
type RRArbiter[T <: Data] = chisel3.util.RRArbiter[T]
type Record = chisel3.Record
type Reset = chisel3.Reset
type SInt = chisel3.SInt
type SeqMem[T <: Data] = SyncReadMem[T]
type SwitchContext[T <: Bits] = chisel3.util.SwitchContext[T]
type UInt = chisel3.UInt
type ValidIO[+T <: Data] = Valid[T]
type Vec[T <: Data] = chisel3.Vec[T]
type VecLike[T <: Data] = chisel3.VecLike[T]
type WhenContext = chisel3.WhenContext

Value Members

val BitPat: chisel3.util.BitPat.type
val Cat: chisel3.util.Cat.type
val Counter: chisel3.util.Counter.type
val Decoupled: chisel3.util.Decoupled.type
val DecoupledIO: chisel3.util.Decoupled.type
val Driver: chisel3.Driver.type
val Fill: chisel3.util.Fill.type
val FillInterleaved: chisel3.util.FillInterleaved.type
val ImplicitConversions: chisel3.util.ImplicitConversions.type
val Input: chisel3.Input.type
val LFSR16: chisel3.util.LFSR16.type
val ListLookup: chisel3.util.ListLookup.type
val Log2: chisel3.util.Log2.type
val Lookup: chisel3.util.Lookup.type
val Mem: chisel3.Mem.type
val Module: chisel3.Module.type
val Mux: chisel3.Mux.type
val Mux1H: chisel3.util.Mux1H.type
val MuxCase: chisel3.util.MuxCase.type
val MuxLookup: chisel3.util.MuxLookup.type
val OHToUInt: chisel3.util.OHToUInt.type
val Output: chisel3.Output.type
val Pipe: chisel3.util.Pipe.type
val PopCount: chisel3.util.PopCount.type
val PriorityEncoder: chisel3.util.PriorityEncoder.type
val PriorityEncoderOH: chisel3.util.PriorityEncoderOH.type
val PriorityMux: chisel3.util.PriorityMux.type
val Queue: chisel3.util.Queue.type
val RegEnable: chisel3.util.RegEnable.type
val RegInit: chisel3.RegInit.type
val RegNext: chisel3.RegNext.type
val Reverse: chisel3.util.Reverse.type
val SeqMem: SyncReadMem.type
val ShiftRegister: chisel3.util.ShiftRegister.type
val UIntToOH: chisel3.util.UIntToOH.type
val Valid: chisel3.util.Valid.type
val assert: chisel3.assert.type
implicit val defaultCompileOptions: CompileOptionsClass
package iotesters

Provide "Chisel" interface to specific chisel3 internals.
val is: chisel3.util.is.type
val isPow2: chisel3.util.isPow2.type
val log2Ceil: chisel3.util.log2Ceil.type
val log2Floor: chisel3.util.log2Floor.type
val printf: chisel3.printf.type
implicit def resetToBool(reset: Reset): Bool
val stop: chisel3.stop.type
val switch: chisel3.util.switch.type
val unless: chisel3.util.unless.type
val when: chisel3.when.type

package Chisel

Type Members

type Aggregate = chisel3.Aggregate

type Arbiter[T <: Data] = chisel3.util.Arbiter[T]

type ArbiterIO[T <: Data] = chisel3.util.ArbiterIO[T]

type BackendCompilationUtilities = firrtl.util.BackendCompilationUtilities

type BitPat = chisel3.util.BitPat

type Bits = chisel3.Bits

type Bool = chisel3.Bool

type Bundle = chisel3.Bundle

type ChiselException = chisel3.internal.ChiselException

type Clock = chisel3.Clock

type Counter = chisel3.util.Counter

type Data = chisel3.Data

type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T]

type Element = chisel3.Element

type LockingArbiter[T <: Data] = chisel3.util.LockingArbiter[T]

type LockingArbiterLike[T <: Data] = chisel3.util.LockingArbiterLike[T]

type LockingRRArbiter[T <: Data] = chisel3.util.LockingRRArbiter[T]

type Mem[T <: Data] = chisel3.Mem[T]

type MemBase[T <: Data] = chisel3.MemBase[T]

type Module = CompatibilityModule

type Num[T <: Data] = chisel3.Num[T]

type Pipe[T <: Data] = chisel3.util.Pipe[T]

type Queue[T <: Data] = QueueCompatibility[T]

type QueueIO[T <: Data] = chisel3.util.QueueIO[T]

type RRArbiter[T <: Data] = chisel3.util.RRArbiter[T]

type Record = chisel3.Record

type Reset = chisel3.Reset

type SInt = chisel3.SInt

type SeqMem[T <: Data] = SyncReadMem[T]

type SwitchContext[T <: Bits] = chisel3.util.SwitchContext[T]

type UInt = chisel3.UInt

type ValidIO[+T <: Data] = Valid[T]

type Vec[T <: Data] = chisel3.Vec[T]

type VecLike[T <: Data] = chisel3.VecLike[T]

type WhenContext = chisel3.WhenContext

Value Members

val BitPat: chisel3.util.BitPat.type

val Cat: chisel3.util.Cat.type

val Counter: chisel3.util.Counter.type

val Decoupled: chisel3.util.Decoupled.type

val DecoupledIO: chisel3.util.Decoupled.type

val Driver: chisel3.Driver.type

val Fill: chisel3.util.Fill.type

val FillInterleaved: chisel3.util.FillInterleaved.type

val ImplicitConversions: chisel3.util.ImplicitConversions.type

val Input: chisel3.Input.type

val LFSR16: chisel3.util.LFSR16.type

val ListLookup: chisel3.util.ListLookup.type

val Log2: chisel3.util.Log2.type

val Lookup: chisel3.util.Lookup.type

val Mem: chisel3.Mem.type

val Module: chisel3.Module.type

val Mux: chisel3.Mux.type

val Mux1H: chisel3.util.Mux1H.type

val MuxCase: chisel3.util.MuxCase.type

val MuxLookup: chisel3.util.MuxLookup.type

val OHToUInt: chisel3.util.OHToUInt.type

val Output: chisel3.Output.type

val Pipe: chisel3.util.Pipe.type

val PopCount: chisel3.util.PopCount.type

val PriorityEncoder: chisel3.util.PriorityEncoder.type

val PriorityEncoderOH: chisel3.util.PriorityEncoderOH.type

val PriorityMux: chisel3.util.PriorityMux.type

val Queue: chisel3.util.Queue.type

val RegEnable: chisel3.util.RegEnable.type

val RegInit: chisel3.RegInit.type

val RegNext: chisel3.RegNext.type

val Reverse: chisel3.util.Reverse.type

val SeqMem: SyncReadMem.type

val ShiftRegister: chisel3.util.ShiftRegister.type

val UIntToOH: chisel3.util.UIntToOH.type

val Valid: chisel3.util.Valid.type

val assert: chisel3.assert.type

implicit val defaultCompileOptions: CompileOptionsClass

package iotesters

val is: chisel3.util.is.type

val isPow2: chisel3.util.isPow2.type