Bundle
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package chisel3
Connect this data to that data mono-directionally and element-wise.
Connect this data to that data mono-directionally and element-wise.
This uses the MonoConnect algorithm.
the data to connect to
Connect this data to that data bi-directionally and element-wise.
Connect this data to that data bi-directionally and element-wise.
This uses the BiConnect algorithm.
the data to connect to
Does a reinterpret cast of the bits in this node into the format that provides.
Does a reinterpret cast of the bits in this node into the format that provides. Returns a new Wire of that type. Does not modify existing nodes.
x.asTypeOf(that) performs the inverse operation of x := that.toBits.
that should have known widths
,bit widths are NOT checked, may pad or drop bits from input
Reinterpret cast to UInt.
Reinterpret cast to UInt.
Aggregates are recursively packed with the first element appearing in the least-significant bits of the result.
,value not guaranteed to be preserved: for example, a SInt of width 3 and value -1 (0b111) would become an UInt with value 7
Takes the last seed suggested.
Takes the last seed suggested. Multiple calls to this function will take the last given seed, unless this HasId is a module port (see overridden method in Data.scala).
If the final computed name conflicts with the final name of another signal, the final name may get uniquified by appending a digit at the end of the name.
Is a lower priority than suggestName, in that regardless of whether autoSeed was called, suggestName will always take precedence if it was called.
this object
Name for Pretty Printing
Internal API; Chisel users should look at chisel3.chiselTypeOf(...).
Computes the name of this HasId, if one exists
Computes the name of this HasId, if one exists
Optionally provide a default prefix for computing the name
Optionally provide default seed for computing the name
the name, if it can be computed
The collection of Data
The collection of Data
Elements defined earlier in the Bundle are higher order upon serialization. For example:
class MyBundle extends Bundle { val foo = UInt(16.W) val bar = UInt(16.W) } // Note that foo is higher order because its defined earlier in the Bundle val bundle = Wire(new MyBundle) bundle.foo := 0x1234.U bundle.bar := 0x5678.U val uint = bundle.asUInt assert(uint === "h12345678".U) // This will pass
Returns a Seq of the immediate contents of this Aggregate, in order.
Returns the width, in bits, if currently known.
Returns the width, in bits, if currently known.
Whether either autoName or suggestName has been called
Overridden by IgnoreSeqInBundle to allow arbitrary Seqs of Chisel elements.
Returns whether the width is currently known.
Returns whether the width is currently known.
Return an Aggregate's literal value if it is a literal, None otherwise.
Returns the literal value if this is a literal that is representable as bits, otherwise crashes.
Returns the literal value if this is a literal that is representable as bits, otherwise crashes.
Takes the first seed suggested.
Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.
Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.
The seed for the name of this component
this object
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
Returns a FIRRTL ComponentName that references this object
Returns a FIRRTL ComponentName that references this object
Should not be called until circuit elaboration is complete
Default "pretty-print" implementation
Analogous to printing a Map
Results in "Bundle(elt0.name -> elt0.value, ...)"
The collection of Data
The collection of Data
This underlying datastructure is a ListMap because the elements must remain ordered for serialization/deserialization. Elements added later are higher order when serialized (this is similar to Vec). For example:
// Assume we have some type MyRecord that creates a Record from the ListMap val record = MyRecord(ListMap("fizz" -> UInt(16.W), "buzz" -> UInt(16.W))) // "buzz" is higher order because it was added later than "fizz" record("fizz") := "hdead".U record("buzz") := "hbeef".U val uint = record.asUInt assert(uint === "hbeefdead".U) // This will pass
Returns a FIRRTL ReferenceTarget that references this object
Returns a FIRRTL ReferenceTarget that references this object
Should not be called until circuit elaboration is complete
Returns Some(width) if the width is known, else None.
Returns Some(width) if the width is known, else None.
Utilities for connecting hardware components
Base class for data types defined as a bundle of other data types.
Usage: extend this class (either as an anonymous or named class) and define members variables of Data subtypes to be elements in the Bundle.
Example of an anonymous IO bundle
Or as a named class