Analog
Related Docs:
object Analog
| package experimental
Connect this data to that data mono-directionally and element-wise.
Connect this data to that data mono-directionally and element-wise.
This uses the MonoConnect algorithm.
the data to connect to
Connect this data to that data bi-directionally and element-wise.
Connect this data to that data bi-directionally and element-wise.
This uses the BiConnect algorithm.
the data to connect to
Does a reinterpret cast of the bits in this node into the format that provides.
Does a reinterpret cast of the bits in this node into the format that provides. Returns a new Wire of that type. Does not modify existing nodes.
x.asTypeOf(that) performs the inverse operation of x := that.toBits.
that should have known widths
,bit widths are NOT checked, may pad or drop bits from input
Reinterpret cast to UInt.
Reinterpret cast to UInt.
Aggregates are recursively packed with the first element appearing in the least-significant bits of the result.
,value not guaranteed to be preserved: for example, a SInt of width 3 and value -1 (0b111) would become an UInt with value 7
Takes the last seed suggested.
Takes the last seed suggested. Multiple calls to this function will take the last given seed, unless this HasId is a module port (see overridden method in Data.scala).
If the final computed name conflicts with the final name of another signal, the final name may get uniquified by appending a digit at the end of the name.
Is a lower priority than suggestName, in that regardless of whether autoSeed was called, suggestName will always take precedence if it was called.
this object
Internal API; Chisel users should look at chisel3.chiselTypeOf(...).
Computes the name of this HasId, if one exists
Computes the name of this HasId, if one exists
Optionally provide a default prefix for computing the name
Optionally provide default seed for computing the name
the name, if it can be computed
Returns the width, in bits, if currently known.
Returns the width, in bits, if currently known.
Whether either autoName or suggestName has been called
Returns whether the width is currently known.
Returns whether the width is currently known.
If this is a literal that is representable as bits, returns the value as a BigInt.
Returns the literal value if this is a literal that is representable as bits, otherwise crashes.
Returns the literal value if this is a literal that is representable as bits, otherwise crashes.
Takes the first seed suggested.
Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.
Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.
The seed for the name of this component
this object
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
Returns a FIRRTL ComponentName that references this object
Returns a FIRRTL ComponentName that references this object
Should not be called until circuit elaboration is complete
Default pretty printing
Returns a FIRRTL ReferenceTarget that references this object
Returns a FIRRTL ReferenceTarget that references this object
Should not be called until circuit elaboration is complete
Returns Some(width) if the width is known, else None.
Returns Some(width) if the width is known, else None.
Utilities for connecting hardware components
Data type for representing bidirectional bitvectors of a given width
Analog support is limited to allowing wiring up of Verilog BlackBoxes with bidirectional (inout) pins. There is currently no support for reading or writing of Analog types within Chisel code.
Given that Analog is bidirectional, it is illegal to assign a direction to any Analog type. It is legal to "flip" the direction (since Analog can be a member of aggregate types) which has no effect.
Analog types are generally connected using the bidirectional attach mechanism, but also support limited bulkconnect
<>. Analog types are only allowed to be bulk connected *once* in a given module. This is to prevent any surprising consequences of last connect semantics.This API is experimental and subject to change