A workaround for default-value overloading problems in Scala, just 'assert(cond, "")'
An elaboration-time assertion, otherwise the same as the above run-time assertion.
Checks for a condition to be valid in the circuit at all times.
Checks for a condition to be valid in the circuit at all times. If the condition evaluates to false, the circuit simulation stops with an error.
Does not fire when in reset (defined as the encapsulating Module's reset). If your definition of reset is not the encapsulating Module's reset, you will need to gate this externally.
May be called outside of a Module (like defined in a function), so functions using assert make the standard Module assumptions (single clock and single reset).
condition, assertion fires (simulation fails) when false
optional message to print when the assertion fires
optional bits to print in the message formatting
currently cannot be used in core Chisel / libraries because macro defs need to be compiled first and the SBT project is not set up to do that