Hardware module that is used to sequence n producers into 1 consumer.
Hardware module that is used to sequence n producers into 1 consumer. Priority is given to lower producer.
val arb = Module(new Arbiter(2, UInt())) arb.io.in(0) <> producer0.io.out arb.io.in(1) <> producer1.io.out consumer.io.in <> arb.io.out
IO bundle definition for an Arbiter, which takes some number of ready-valid inputs and outputs (selects) at most one.
Bit patterns are literals with masks, used to represent values with don't care bits.
Bit patterns are literals with masks, used to represent values with don't care bits. Equality comparisons will ignore don't care bits.
"b10101".U === BitPat("b101??") // evaluates to true.B "b10111".U === BitPat("b101??") // evaluates to true.B "b10001".U === BitPat("b101??") // evaluates to false.B
A counter module
A counter module
A concrete subclass of ReadyValidIO signaling that the user expects a "decoupled" interface: 'valid' indicates that the producer has put valid data in 'bits', and 'ready' indicates that the consumer is ready to accept the data this cycle.
A concrete subclass of ReadyValidIO signaling that the user expects a "decoupled" interface: 'valid' indicates that the producer has put valid data in 'bits', and 'ready' indicates that the consumer is ready to accept the data this cycle. No requirements are placed on the signaling of ready or valid.
A concrete subclass of ReadyValidIO that promises to not change the value of 'bits' after a cycle where 'valid' is high and 'ready' is low.
A concrete subclass of ReadyValidIO that promises to not change the value of 'bits' after a cycle where 'valid' is high and 'ready' is low. Additionally, once 'valid' is raised it will never be lowered until after 'ready' has also been raised.
A hardware module implementing a Queue
A hardware module implementing a Queue
val q = new Queue(UInt(), 16) q.io.enq <> producer.io.out consumer.io.in <> q.io.deq
An I/O Bundle for Queues
Hardware module that is used to sequence n producers into 1 consumer.
Hardware module that is used to sequence n producers into 1 consumer. Producers are chosen in round robin order.
val arb = new RRArbiter(2, UInt()) arb.io.in(0) <> producer0.io.out arb.io.in(1) <> producer1.io.out consumer.io.in <> arb.io.out
An I/O Bundle containing 'valid' and 'ready' signals that handshake the transfer of data stored in the 'bits' subfield.
An I/O Bundle containing 'valid' and 'ready' signals that handshake the transfer of data stored in the 'bits' subfield. The base protocol implied by the directionality is that the consumer uses the flipped interface. Actual semantics of ready/valid are enforced via use of concrete subclasses.
Implementation details for switch.
An Bundle containing data and a signal determining if it is valid
Synonyms, moved from main package object - maintain scope.
Concatenates elements of the input, in order, together.
Concatenates elements of the input, in order, together.
Cat("b101".U, "b11".U) // equivalent to "b101 11".U Cat(myUIntWire0, myUIntWire1) Cat(Seq("b101".U, "b11".U)) // equivalent to "b101 11".U Cat(mySeqOfBits)
This factory adds a decoupled handshaking protocol to a data bundle.
Create repetitions of the input using a tree fanout topology.
Create repetitions of the input using a tree fanout topology.
Fill(2, "b1000".U) // equivalent to "b1000 1000".U Fill(2, "b1001".U) // equivalent to "b1001 1001".U Fill(2, myUIntWire) // dynamic fill
Creates repetitions of each bit of the input in order.
Creates repetitions of each bit of the input in order.
FillInterleaved(2, "b1 0 0 0".U) // equivalent to "b11 00 00 00".U FillInterleaved(2, "b1 0 0 1".U) // equivalent to "b11 00 00 11".U FillInterleaved(2, myUIntWire) // dynamic interleaved fill FillInterleaved(2, Seq(true.B, false.B, false.B, false.B)) // equivalent to "b11 00 00 00".U FillInterleaved(2, Seq(true.B, false.B, false.B, true.B)) // equivalent to "b11 00 00 11".U
Factory adds an irrevocable handshaking protocol to a data bundle.
Returns the base-2 integer logarithm of an UInt.
Returns the base-2 integer logarithm of an UInt.
Log2(8.U) // evaluates to 3.U Log2(13.U) // evaluates to 3.U (truncation) Log2(myUIntWire)
The result is truncated, so e.g. Log2(13.U) === 3.U
Builds a Mux tree out of the input signal vector using a one hot encoded select signal.
Builds a Mux tree out of the input signal vector using a one hot encoded select signal. Returns the output of the Mux tree.
results undefined if multiple select signals are simultaneously high
Given an association of values to enable signals, returns the first value with an associated high enable signal.
Creates a cascade of n Muxs to search for a key value.
Returns the bit position of the sole high bit of the input bitvector.
Returns the bit position of the sole high bit of the input bitvector.
Inverse operation of UIntToOH.
assumes exactly one high bit, results undefined otherwise
A hardware module that delays data coming down the pipeline by the number of cycles set by the latency parameter.
A hardware module that delays data coming down the pipeline by the number of cycles set by the latency parameter. Functionality is similar to ShiftRegister but this exposes a Pipe interface.
Example usage: val pipe = new Pipe(UInt()) pipe.io.enq <> produce.io.out consumer.io.in <> pipe.io.deq
Returns the number of bits set (value is 1 or true) in the input signal.
Returns the number of bits set (value is 1 or true) in the input signal.
PopCount(Seq(true.B, false.B, true.B, true.B)) // evaluates to 3.U PopCount(Seq(false.B, false.B, true.B, false.B)) // evaluates to 1.U PopCount("b1011".U) // evaluates to 3.U PopCount("b0010".U) // evaluates to 1.U PopCount(myUIntWire) // dynamic count
Returns the bit position of the least-significant high bit of the input bitvector.
Returns the bit position of the least-significant high bit of the input bitvector.
Multiple bits may be high in the input.
Returns a bit vector in which only the least-significant 1 bit in the input vector, if any, is set.
Builds a Mux tree under the assumption that multiple select signals can be enabled.
Builds a Mux tree under the assumption that multiple select signals can be enabled. Priority is given to the first select signal.
Returns the output of the Mux tree.
Factory for a generic hardware queue.
Factory for a generic hardware queue.
output (dequeue) interface from the queue
consumer.io.in <> Queue(producer.io.out, 16)
Returns the input in bit-reversed order.
Returns the input in bit-reversed order. Useful for little/big-endian conversion.
Reverse("b1101".U) // equivalent to "b1011".U Reverse("b1101".U(8.W)) // equivalent to "b10110000".U Reverse(myUIntWire) // dynamic reverse
The purpose of TransitName is to allow a library to 'move' a name call to a more appropriate place.
The purpose of TransitName is to allow a library to 'move' a name call to a more appropriate place. For example, a library factory function may create a module and return the io. The only user-exposed field is that given IO, which can't use any name supplied by the user. This can add a hook so that the supplied name then names the Module. See Queue companion object for working example
Returns the one hot encoding of the input UInt.
Adds a valid protocol to any interface
Use to specify cases in a switch block, equivalent to a when block comparing to the condition variable.
Check if an Integer is a power of 2
Compute the log2 rounded up
Compute the log2 rounded down
Conditional logic to form a switch block.
Conditional logic to form a switch block. See is for the case API.
switch (myState) { is (state1) { // some logic here that runs when myState === state1 } is (state2) { // some logic here that runs when myState === state2 } }
Compute the log2 rounded down with min value of 1
Compute the log2 rounded down with min value of 1
(Since version chisel3) Use log2Floor instead
Compute the log2 rounded up with min value of 1
Compute the log2 rounded up with min value of 1
(Since version chisel3) Use log2Ceil instead
The util package provides extensions to core chisel for common hardware components and utility functions.