ExtModule
Related Doc:
package core
This must wrap the datatype used to set the io field of any Module.
This must wrap the datatype used to set the io field of any Module. i.e. All concrete modules must have defined io in this form: [lazy] val io[: io type] = IO(...[: io type])
Items in [] are optional.
The granted iodef WILL NOT be cloned (to allow for more seamless use of anonymous Bundles in the IO) and thus CANNOT have been bound to any logic. This will error if any node is bound (e.g. due to logic in a Bundle constructor, which is considered improper).
Also registers a Data as a port, also performing bindings. Cannot be called once ports are requested (so that all calls to ports will return the same information). Internal API.
TODO(twigg): Specifically walk the Data definition to call out which nodes are problematic.
Compatibility function.
Compatibility function. Allows Chisel2 code which had ports without the IO wrapper to compile under Bindings checks. Does nothing in non-compatibility mode.
Should NOT be used elsewhere. This API will NOT last.
TODO: remove this, perhaps by removing Bindings checks in compatibility mode.
Desired name of this module.
Desired name of this module. Override this to give this module a custom, perhaps parametric, name.
Signal name (for simulation).
Signal name (for simulation).
Legalized name of this module.
Legalized name of this module.
Called at the Module.apply(...) level after this Module has finished elaborating.
Called at the Module.apply(...) level after this Module has finished elaborating. Returns a map of nodes -> names, for named nodes.
Helper method.
Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog. Useful for connecting to RTL modules defined outside Chisel.
A variant of BlackBox, this has a more consistent naming scheme in allowing multiple top-level IO and does not drop the top prefix.
Some design require a differential input clock to clock the all design. With the xilinx FPGA for example, a Verilog template named IBUFDS must be integrated to use differential input:
To instantiate it, a BlackBox can be used like following:
The parameters API is experimental and may change