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Value Members

1. final def !=(arg0: Any): Boolean

   

   Definition Classes

   AnyRef → Any

2. final def ##(): Int

   

   Definition Classes

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3. final def ==(arg0: Any): Boolean

   

   Definition Classes

   AnyRef → Any

4. lazy val TestDirectory: File

   

   Definition Classes

   BackendCompilationUtilities

5. final def asInstanceOf[T0]: T0

   

   Definition Classes

   Any

6. val chiselVersionString: String

   

7. def clone(): AnyRef

   

   Attributes

   protected[java.lang]

   Definition Classes

   AnyRef

   Annotations

   @throws( ... )

8. def compileFirrtlToVerilog(prefix: String, dir: File): Boolean

   

   Compile Chirrtl to Verilog by invoking Firrtl inside the same JVM

   Compile Chirrtl to Verilog by invoking Firrtl inside the same JVM

   prefix

   basename of the file

   dir

   directory where file lives

   returns

   true if compiler completed successfully

   Definition Classes

   BackendCompilationUtilities

9. def copyResourceToFile(name: String, file: File): Unit

   

   Definition Classes

   BackendCompilationUtilities

10. def cppToExe(prefix: String, dir: File): ProcessBuilder

    

    Definition Classes

    BackendCompilationUtilities

11. def createTestDirectory(testName: String): File

    

    Definition Classes

    BackendCompilationUtilities

12. def dumpFirrtl(ir: Circuit, optName: Option[File]): File

    

13. def elaborate[T <: RawModule](gen: () ⇒ T): Circuit

    

    Elaborates the Module specified in the gen function into a Circuit

    Elaborates the Module specified in the gen function into a Circuit

    gen

    a function that creates a Module hierarchy

    returns

    the resulting Chisel IR in the form of a Circuit (TODO: Should be FIRRTL IR)

14. def emit[T <: RawModule](ir: Circuit): String

    

15. def emit[T <: RawModule](gen: () ⇒ T): String

    

16. def emitVerilog[T <: RawModule](gen: ⇒ T): String

    

    Elaborates the Module specified in the gen function into Verilog

    Elaborates the Module specified in the gen function into Verilog

    gen

    a function that creates a Module hierarchy

    returns

    the resulting String containing the design in Verilog

17. final def eq(arg0: AnyRef): Boolean

    

    Definition Classes

    AnyRef

18. def equals(arg0: Any): Boolean

    

    Definition Classes

    AnyRef → Any

19. def execute(args: Array[String], dut: () ⇒ RawModule): ChiselExecutionResult

    

    Run the chisel3 compiler and possibly the firrtl compiler with options specified via an array of Strings

    Run the chisel3 compiler and possibly the firrtl compiler with options specified via an array of Strings

    args

    The options specified, command line style

    dut

    The device under test

    returns

    An execution result with useful stuff, or failure with message

20. def execute(optionsManager: ExecutionOptionsManager with HasChiselExecutionOptions with HasFirrtlOptions, dut: () ⇒ RawModule): ChiselExecutionResult

    

    Run the chisel3 compiler and possibly the firrtl compiler with options specified

    Run the chisel3 compiler and possibly the firrtl compiler with options specified

    optionsManager

    The options specified

    dut

    The device under test

    returns

    An execution result with useful stuff, or failure with message

21. def executeExpectingFailure(prefix: String, dir: File, assertionMsg: String): Boolean

    

    Definition Classes

    BackendCompilationUtilities

22. def executeExpectingSuccess(prefix: String, dir: File): Boolean

    

    Definition Classes

    BackendCompilationUtilities

23. def finalize(): Unit

    

    Attributes

    protected[java.lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( classOf[java.lang.Throwable] )

24. def firrtlToVerilog(prefix: String, dir: File): ProcessBuilder

    

    Definition Classes

    BackendCompilationUtilities

25. final def getClass(): Class[_]

    

    Definition Classes

    AnyRef → Any

26. def hashCode(): Int

    

    Definition Classes

    AnyRef → Any

27. final def isInstanceOf[T0]: Boolean

    

    Definition Classes

    Any

28. def main(args: Array[String]): Unit

    

    This is just here as command line way to see what the options are It will not successfully run TODO: Look into dynamic class loading as way to make this main useful

    This is just here as command line way to see what the options are It will not successfully run TODO: Look into dynamic class loading as way to make this main useful

    args

    unused args

29. def makeHarness(template: (String) ⇒ String, post: String)(f: File): File

    

    Definition Classes

    BackendCompilationUtilities

30. final def ne(arg0: AnyRef): Boolean

    

    Definition Classes

    AnyRef

31. final def notify(): Unit

    

    Definition Classes

    AnyRef

32. final def notifyAll(): Unit

    

    Definition Classes

    AnyRef

33. def parseArgs(args: Array[String]): Unit

    

34. final def synchronized[T0](arg0: ⇒ T0): T0

    

    Definition Classes

    AnyRef

35. def targetDir(): String

    

36. def timeStamp: String

    

    Definition Classes

    BackendCompilationUtilities

37. def toString(): String

    

    Definition Classes

    AnyRef → Any

38. def verilogToCpp(dutFile: String, dir: File, vSources: Seq[File], cppHarness: File): ProcessBuilder

    

    Definition Classes

    BackendCompilationUtilities

39. val version: String

    

40. final def wait(): Unit

    

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

41. final def wait(arg0: Long, arg1: Int): Unit

    

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

42. final def wait(arg0: Long): Unit

    

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )