Compile Chirrtl to Verilog by invoking Firrtl inside the same JVM
Compile Chirrtl to Verilog by invoking Firrtl inside the same JVM
basename of the file
directory where file lives
true if compiler completed successfully
Elaborates the Module specified in the gen function into a Circuit
Elaborates the Module specified in the gen function into a Circuit
a function that creates a Module hierarchy
the resulting Chisel IR in the form of a Circuit (TODO: Should be FIRRTL IR)
Elaborates the Module specified in the gen function into Verilog
Elaborates the Module specified in the gen function into Verilog
a function that creates a Module hierarchy
the resulting String containing the design in Verilog
Run the chisel3 compiler and possibly the firrtl compiler with options specified via an array of Strings
Run the chisel3 compiler and possibly the firrtl compiler with options specified via an array of Strings
The options specified, command line style
The device under test
An execution result with useful stuff, or failure with message
Run the chisel3 compiler and possibly the firrtl compiler with options specified
Run the chisel3 compiler and possibly the firrtl compiler with options specified
The options specified
The device under test
An execution result with useful stuff, or failure with message
This is just here as command line way to see what the options are It will not successfully run TODO: Look into dynamic class loading as way to make this main useful
This is just here as command line way to see what the options are It will not successfully run TODO: Look into dynamic class loading as way to make this main useful
unused args