PRNG

abstract def delta(s: Seq[Bool]): Seq[Bool]

State update function

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

def IO[T <: Data](iodef: T): T

def _bindIoInPlace(iodef: Data): Unit

var _closed: Boolean

def _compatAutoWrapPorts(): Unit

def _compatIoPortBound(): Boolean

final def asInstanceOf[T0]: T0

def circuitName: String

val clock: Clock

def clone(): AnyRef

val compileOptions: CompileOptions

def desiredName: String

final def eq(arg0: AnyRef): Boolean

def equals(that: Any): Boolean

def finalize(): Unit

final def getClass(): Class[_]

def getCommands: Seq[Command]

def getIds: Seq[HasId]

def getModulePorts: Seq[Data]

lazy val getPorts: Seq[Port]

def hashCode(): Int

def instanceName: String

val io: PRNGIO

final def isInstanceOf[T0]: Boolean

final lazy val name: String

def nameIds(rootClass: Class[_]): HashMap[HasId, String]

final def ne(arg0: AnyRef): Boolean

final def nextState(s: Seq[Bool]): Seq[Bool]

The method that will be used to update the state of this PRNG

final def notify(): Unit

final def notifyAll(): Unit

var override_clock: Option[Clock]

var override_reset: Option[Bool]

def parentModName: String

def parentPathName: String

def pathName: String

def portsContains(elem: Data): Boolean

def portsSize: Int

val reset: Reset

def resetValue: Vec[Bool]

Allow implementations to override the reset value, e.g., if some bits should be don't-cares.

val seed: Option[BigInt]

the initial state of the PRNG

def suggestName(name: ⇒ String): PRNG.this.type

final def synchronized[T0](arg0: ⇒ T0): T0

final def toAbsoluteTarget: IsModule

def toString(): String

final def toTarget: ModuleTarget

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

val width: Int

the width of the PRNG

final def toNamed: ModuleName