Driver
Related Doc:
package chisel3
Compile Chirrtl to Verilog by invoking Firrtl inside the same JVM
Compile Chirrtl to Verilog by invoking Firrtl inside the same JVM
basename of the file
directory where file lives
true if compiler completed successfully
Emit the annotations of a circuit
Emit the annotations of a circuit
The circuit containing annotations to be emitted
An optional filename (will use s"${ir.name}.json" otherwise)
Dump the elaborated Chisel IR Circuit as a FIRRTL String, without invoking FIRRTL.
Dump the elaborated Chisel IR Circuit as a FIRRTL String, without invoking FIRRTL.
If no File is given as input, it will dump to a default filename based on the name of the top Module.
File to dump to. If unspecified, defaults to "<topmodule>.fir".
The File the circuit was dumped to.
Dump the elaborated Circuit to ProtoBuf.
Dump the elaborated Circuit to ProtoBuf.
If no File is given as input, it will dump to a default filename based on the name of the top Module.
Elaborated Chisel Circuit.
Optional File to dump to. If unspecified, defaults to "<topmodule>.pb".
The File the circuit was dumped to.
Elaborate the Module specified in the gen function into a Chisel IR Circuit.
Elaborate the Module specified in the gen function into a Chisel IR Circuit.
A function that creates a Module hierarchy.
The resulting Chisel IR in the form of a Circuit. (TODO: Should be FIRRTL IR)
Emit the given Chisel IR Circuit as a FIRRTL string, without invoking FIRRTL.
Emit the given Chisel IR Circuit as a FIRRTL string, without invoking FIRRTL.
Chisel IR Circuit, generated e.g. by elaborate().
Emit the Module specified in the gen function directly as a FIRRTL string without invoking FIRRTL.
Emit the Module specified in the gen function directly as a FIRRTL string without invoking FIRRTL.
A function that creates a Module hierarchy.
Elaborate the Module specified in the gen function into Verilog.
Elaborate the Module specified in the gen function into Verilog.
A function that creates a Module hierarchy.
A String containing the design in Verilog.
Run the chisel3 compiler and possibly the firrtl compiler with options specified via an array of Strings
Run the chisel3 compiler and possibly the firrtl compiler with options specified via an array of Strings
The options specified, command line style
The device under test
An execution result with useful stuff, or failure with message
Run the chisel3 compiler and possibly the firrtl compiler with options specified
Run the chisel3 compiler and possibly the firrtl compiler with options specified
The options specified
The device under test
An execution result with useful stuff, or failure with message
This is just here as command line way to see what the options are It will not successfully run TODO: Look into dynamic class loading as way to make this main useful
This is just here as command line way to see what the options are It will not successfully run TODO: Look into dynamic class loading as way to make this main useful
unused args
Convert the given Chisel IR Circuit to a FIRRTL Circuit.
Convert the given Chisel IR Circuit to a FIRRTL Circuit.
Chisel IR Circuit, generated e.g. by elaborate().