This transform only is activated if Verilog is being generated (determined by presence of the proper emit
annotation) when activated it creates additional Verilog files that contain modules bound to the modules that
contain an initializable memory
Currently the only non-Verilog based simulation that can support loading memory from a file is treadle but it does
not need this transform to do that.
This transform only is activated if Verilog is being generated (determined by presence of the proper emit annotation) when activated it creates additional Verilog files that contain modules bound to the modules that contain an initializable memory
Currently the only non-Verilog based simulation that can support loading memory from a file is treadle but it does not need this transform to do that.