HasExtModuleInline

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

def IO[T <: Data](iodef: T): T

def _bindIoInPlace(iodef: Data): Unit

var _closed: Boolean

def _compatAutoWrapPorts(): Unit

final def asInstanceOf[T0]: T0

def circuitName: String

def clone(): AnyRef

def computeName(defaultPrefix: Option[String], defaultSeed: Option[String]): Option[String]

def desiredName: String

final def eq(arg0: AnyRef): Boolean

def equals(that: Any): Boolean

final def getClass(): Class[_]

def getIds: Seq[HasId]

def getModulePorts: Seq[Data]

def hasSeed: Boolean

def hashCode(): Int

def instanceName: String

final def isInstanceOf[T0]: Boolean

final lazy val name: String

def nameIds(rootClass: Class[_]): HashMap[HasId, String]

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

val params: Map[String, Param]

def parentModName: String

def parentPathName: String

def pathName: String

def portsContains(elem: Data): Boolean

def portsSize: Int

def setInline(blackBoxName: String, blackBoxInline: String): Unit

Creates a black box verilog file, from the contents of a local string

def suggestName(seed: ⇒ String): HasExtModuleInline.this

final def synchronized[T0](arg0: ⇒ T0): T0

final def toAbsoluteTarget: IsModule

final def toNamed: ModuleName

def toString(): String

final def toTarget: ModuleTarget

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

final def wait(): Unit

def finalize(): Unit