object LFSR16
LFSR16 generates a 16-bit linear feedback shift register, returning the register contents. This is useful for generating a pseudo-random sequence.
The example below, taken from the unit tests, creates two 4-sided dice using LFSR16
primitives:
- Annotations
- @nowarn()
- Source
- compatibility.scala
val bins = Reg(Vec(8, UInt(32.W))) // Create two 4 sided dice and roll them each cycle. // Use tap points on each LFSR so values are more independent val die0 = Cat(Seq.tabulate(2) { i => LFSR16()(i) }) val die1 = Cat(Seq.tabulate(2) { i => LFSR16()(i + 2) }) val rollValue = die0 +& die1 // Note +& is critical because sum will need an extra bit. bins(rollValue) := bins(rollValue) + 1.U
Example:
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- def apply(increment: Bool = true.B): UInt
Generates a 16-bit linear feedback shift register, returning the register contents.
Generates a 16-bit linear feedback shift register, returning the register contents.
- increment
optional control to gate when the LFSR updates.
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- @deprecated
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(Since version Chisel 3.6) Chisel compatibility mode is deprecated. Use the chisel3 package instead.
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This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt
,SInt
,Bool
,FixedPoint
,Clock
, andReg
, the abstract typesBits
,Aggregate
, andData
, and the aggregate typesBundle
andVec
.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
util
package.The
testers
package defines the basic interface for chisel testers.