FPGABackend

Value Members

1. final def !=(arg0: AnyRef): Boolean

   Definition Classes

   AnyRef

2. final def !=(arg0: Any): Boolean

   Definition Classes

   Any

3. final def ##(): Int

   Definition Classes

   AnyRef → Any

4. final def ==(arg0: AnyRef): Boolean

   Definition Classes

   AnyRef

5. final def ==(arg0: Any): Boolean

   Definition Classes

   Any

6. final def asInstanceOf[T0]: T0

   Definition Classes

   Any

7. def asValidName(name: String): String

   Definition Classes

   Backend

8. def assignClockAndResetToModules: Unit

   Definition Classes

   Backend

9. def checkPorts(topC: Module): Unit

   Definition Classes

   Backend

10. def clone(): AnyRef

    Attributes

    protected[java.lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

11. def collectNodesIntoComp(dfsStack: Stack[Node]): Unit

    Nodes which are created outside the execution trace from the toplevel component constructor (i.

    Nodes which are created outside the execution trace from the toplevel component constructor (i.e. through the () => Module(new Top()) ChiselMain argument) will have a component field set to null. For example, genMuxes, forceMatchWidths and transforms (all called from Backend.elaborate) create such nodes.

    This method walks all nodes from all component roots (outputs, debugs). and reassociates the component to the node both ways (i.e. in Module.nodes and Node.component).

    We assume here that all nodes at the components boundaries (io) have a non-null and correct node/component association. We further assume that nodes generated in elaborate are inputs to a node whose component field is set.

    Implementation Node: At first we did implement *collectNodesIntoComp* to handle a single component at a time but that did not catch the cases where Regs are passed as input to sub-module without being tied to an output of *this.component*.

    Definition Classes

    Backend

12. val compIndices: HashMap[String, Int]

    Definition Classes

    VerilogBackend

13. def compile(c: Module, flags: String): Unit

    Definition Classes

    VerilogBackend → Backend

14. def connectResets: Unit

    Definition Classes

    Backend

15. def createClkDomain(root: Node, walked: ArrayBuffer[Node]): Unit

    Definition Classes

    Backend

16. def createOutputFile(name: String): FileWriter

    Definition Classes

    Backend

17. def depthString(depth: Int): String

    Definition Classes

    Backend

18. def doCompile(top: Module, out: FileWriter, depth: Int): Unit

    Definition Classes

    VerilogBackend

19. def elaborate(c: Module): Unit

    Definition Classes

    VerilogBackend → Backend

20. def emitChildren(top: Module, defs: HashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], out: FileWriter, depth: Int): Unit

    Definition Classes

    VerilogBackend

21. def emitDec(node: Node): String

    Definition Classes

    FPGABackend → VerilogBackend → Backend

22. def emitDecBase(node: Node): String

    Definition Classes

    VerilogBackend

23. def emitDecs(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

24. def emitDef(node: Node): String

    Definition Classes

    FPGABackend → VerilogBackend → Backend

25. def emitDef(c: Module): String

    Definition Classes

    VerilogBackend

26. def emitDefs(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

27. def emitModuleText(c: Module): String

    Definition Classes

    VerilogBackend

28. def emitPortDef(m: MemAccess, idx: Int): String

    Definition Classes

    VerilogBackend

29. def emitRef(node: Node): String

    Definition Classes

    VerilogBackend → Backend

30. def emitRef(c: Module): String

    Definition Classes

    Backend

31. def emitReg(node: Node): String

    Definition Classes

    FPGABackend → VerilogBackend

32. def emitRegs(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

33. def emitSigned(n: Node): String

    Definition Classes

    VerilogBackend

34. def emitTmp(node: Node): String

    Definition Classes

    VerilogBackend → Backend

35. def emitWidth(node: Node): String

    Definition Classes

    VerilogBackend

36. def ensureDir(dir: String): String

    Ensures a directory *dir* exists on the filesystem.

    Ensures a directory *dir* exists on the filesystem.

    Definition Classes

    Backend

37. final def eq(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef

38. def equals(arg0: Any): Boolean

    Definition Classes

    AnyRef → Any

39. def extractClassName(comp: Module): String

    Definition Classes

    Backend

40. def finalize(): Unit

    Attributes

    protected[java.lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( classOf[java.lang.Throwable] )

41. def flushModules(out: FileWriter, defs: HashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], level: Int): Unit

    Definition Classes

    VerilogBackend

42. val flushedTexts: HashSet[String]

    Definition Classes

    VerilogBackend

43. def fullyQualifiedName(m: Node): String

    Definition Classes

    Backend

44. def gatherChildren(root: Module): ArrayBuffer[Module]

    Definition Classes

    Backend

45. def gatherClocksAndResets: Unit

    Definition Classes

    Backend

46. def genHarness(c: Module, name: String): Unit

    Definition Classes

    VerilogBackend

47. def genIndent(x: Int): String

    Attributes

    protected

    Definition Classes

    Backend

48. final def getClass(): Class[_]

    Definition Classes

    AnyRef → Any

49. def hashCode(): Int

    Definition Classes

    AnyRef → Any

50. def initializeDFS: Stack[Node]

    Definition Classes

    Backend

51. final def isInstanceOf[T0]: Boolean

    Definition Classes

    Any

52. def isMultiWrite(m: Mem[_]): Boolean

53. val keywords: HashSet[String]

    Definition Classes

    VerilogBackend → Backend

54. def levelChildren(root: Module): Unit

    Definition Classes

    Backend

55. val memConfs: HashMap[String, String]

    Definition Classes

    VerilogBackend

56. def nameAll(root: Module): Unit

    Definition Classes

    Backend

57. def nameChildren(root: Module): Unit

    Definition Classes

    Backend

58. def nameRsts: Unit

    Definition Classes

    Backend

59. final def ne(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef

60. final def notify(): Unit

    Definition Classes

    AnyRef

61. final def notifyAll(): Unit

    Definition Classes

    AnyRef

62. def printStack: Unit

    Prints the call stack of Component as seen by the push/pop runtime.

    Prints the call stack of Component as seen by the push/pop runtime.

    Attributes

    protected

    Definition Classes

    Backend

63. def pruneNodes: Unit

    Definition Classes

    Backend

64. def pruneUnconnectedIOs(m: Module): Unit

    Definition Classes

    Backend

65. final def synchronized[T0](arg0: ⇒ T0): T0

    Definition Classes

    AnyRef

66. def toString(): String

    Definition Classes

    AnyRef → Any

67. def transform(c: Module, transforms: ArrayBuffer[(Module) ⇒ Unit]): Unit

    Definition Classes

    Backend

68. val transforms: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes

    Backend

69. final def wait(): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

70. final def wait(arg0: Long, arg1: Int): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

71. final def wait(arg0: Long): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

72. def writeMap(m: Mem[_], exclude: Int = 1): Seq[String]

73. def writen(m: MemWrite): Int