Chisel

Type Members

abstract class AccessTracker extends Delay
abstract class Aggregate extends Data
class Arbiter[T <: Data] extends LockingArbiter[T]

Hardware module that is used to sequence n producers into 1 consumer.
class ArbiterIO[T <: Data] extends Bundle
class Assert extends Node
class AsyncFifo[T <: Data] extends Module
abstract class Backend extends AnyRef
class Binding extends Node
abstract class Bits extends Data with proc

Base class for built-in Chisel types Bits and SInt.
class BitsInObject extends UInt
abstract class BlackBox extends Module
class Bool extends UInt
class Bundle extends Aggregate

Defines a collection of datum of different types into a single coherent whole.
class CSENode extends AnyRef
abstract class Cell extends nameable
class ChiselError extends AnyRef
class ChiselException extends Exception
class Clock extends Node
class CppBackend extends Backend
class CppVertex extends AnyRef
abstract class Data extends Node

*Data* is part of the *Node* Composite Pattern class hierarchy.
class Dbl extends Bits with Num[Dbl]
class DecoupledIO[T <: Data] extends Bundle
class DecoupledIOC[+T <: Data] extends Bundle
class Delay extends Node
class DeqIO[T <: Data] extends DecoupledIO[T]
class DotBackend extends Backend
class EnqIO[T <: Data] extends DecoupledIO[T]
case class EnumParam(value: String, values: List[String]) extends Param[String] with Product with Serializable
class Extract extends Node
class FPGABackend extends VerilogBackend
class Flo extends Bits with Num[Flo]
class FloBackend extends Backend
trait IODirection extends AnyRef
class Literal extends Node

Stores the actual value of a scala literal as a string.
class LockingArbiter[T <: Data] extends LockingArbiterLike[T]
abstract class LockingArbiterLike[T <: Data] extends Module
class LockingRRArbiter[T <: Data] extends LockingArbiterLike[T]
class Log2 extends Node
class MapTester[+T <: Module] extends Tester[T]
class Mem[T <: Data] extends AccessTracker with VecLike[T]
abstract class MemAccess extends Node
class MemRead extends MemAccess
class MemReadWrite extends MemAccess
class MemSeqRead extends MemAccess
class MemWrite extends MemAccess
class ModularCppBackend extends CppBackend
abstract class Module extends AnyRef
class Mux extends Op
abstract class Node extends nameable

*Node* defines the root class of the class hierarchy for a [Composite Pattern](http://en.
trait Num[T <: Data] extends AnyRef
class Op extends Node
abstract class Param[+T] extends AnyRef
class Pipe[T <: Data] extends Module
class Printf extends PrintfBase
class PrintfBase extends Node
class PutativeMemWrite extends Node with proc
class Queue[T <: Data] extends Module
class QueueIO[T <: Data] extends Bundle
class ROM[T <: Data] extends Vec[T]
class ROMRead[T <: Data] extends Node
class RRArbiter[T <: Data] extends LockingRRArbiter[T]

Hardware module that is used to sequence n producers into 1 consumer.
case class RangeParam(value: Int, min: Int, max: Int, step: Int = 1, log: Boolean = false) extends Param[Int] with Product with Serializable
class Reg extends Delay with proc
class SInt extends Bits with Num[SInt]
class Sprintf extends PrintfBase
class TestIO extends AnyRef
class Tester[+T <: Module] extends AnyRef
class UInt extends Bits with Num[UInt]
class ValidIO[+T <: Data] extends Bundle
case class ValueParam(value: Any) extends Param[Any] with Product with Serializable
class VcdBackend extends Backend
class Vec[T <: Data] extends Aggregate with VecLike[T] with Cloneable
trait VecLike[T <: Data] extends IndexedSeq[T]
class VecProc extends Node with proc
class VerilogBackend extends Backend
trait nameable extends AnyRef
trait proc extends Node
class when extends AnyRef

Value Members

object ACos
object ASin
object ATan
object ArbiterCtrl
object Backend
object BinaryBoolOp
object BinaryOp
object Binding
object Bits
object Bool
object Bundle
object CSE
object CString
object Cat
object Ceil
object ChiselError

This Singleton implements a log4j compatible interface.
object Concatenate
object Cos
object Counter
object Dbl
object Decoupled

Adds a ready-valid handshaking protocol to any interface.
object Enum
object Extract
object Fill
object FillInterleaved
object Flo
object Floor
object INPUT extends IODirection
object ImplicitConversions
object IntParam
object LFSR16

linear feedback shift register
object ListLookup
object Lit
object Literal
object Log
object Log2
object LogicalOp
object Lookup
object Mem

*seqRead* means that if a port tries to read the same address that another port is writing to in the same cycle, the read data is random garbage (from a LFSR, which returns "1" on its first invocation).
object Module
object Multiplex
object Mux
object Mux1H

Builds a Mux tree out of the input signal vector using a one hot encoded select signal.
object MuxCase
object MuxLookup
object Node
object NodeExtract
object NodeFill
object OHToUInt

Does the inverse of UIntToOH.
object OUTPUT extends IODirection
object Op
object Params
object Pipe

A hardware module that delays data coming down the pipeline by the number of cycles set by the latency parameter.
object PopCount

Returns the number of bits set (i.
object Pow
object Printer
object PriorityEncoder

Returns the bit position of the trailing 1 in the input vector with the assumption that multiple bits of the input bit vector can be set
object PriorityEncoderOH

Returns a bit vector in which only the least-significant 1 bit in the input vector, if any, is set.
object PriorityMux

Builds a Mux tree under the assumption that multiple select signals can be enabled.
object Queue

Generic hardware queue.
object ReductionOp
object Reg
object RegEnable
object RegInit
object RegNext
object Reverse

Litte/big bit endian convertion: reverse the order of the bits in a UInt.
object Round
object SInt
object Scanner
object ShiftRegister

Returns the n-cycle delayed version of the input signal.
object Sin
object Sqrt
object Tan
object UInt
object UIntToOH

Returns the one hot encoding of the input UInt.
object UnaryOp
object Valid

Adds a valid protocol to any interface.
object Vec
object VecMux
object VecUIntToOH
object VerilogBackend
object andR
object bfs
object chiselCast
object chiselMain

_chiselMain_ behaves as if it constructs an execution tree from the constructor of a sub class of Module which is passed as a parameter.
object chiselMainTest
object foldR
object is
object isLessThan
object isPow2
object log2Down
object log2Up
object orR
object sort
object switch
object throwException
object unless
object when
object xorR

package Chisel

Type Members

abstract class AccessTracker extends Delay

abstract class Aggregate extends Data

class Arbiter[T <: Data] extends LockingArbiter[T]

class ArbiterIO[T <: Data] extends Bundle

class Assert extends Node

class AsyncFifo[T <: Data] extends Module

abstract class Backend extends AnyRef

class Binding extends Node

abstract class Bits extends Data with proc

class BitsInObject extends UInt

abstract class BlackBox extends Module

class Bool extends UInt

class Bundle extends Aggregate

class CSENode extends AnyRef

abstract class Cell extends nameable

class ChiselError extends AnyRef

class ChiselException extends Exception

class Clock extends Node

class CppBackend extends Backend

class CppVertex extends AnyRef

abstract class Data extends Node

class Dbl extends Bits with Num[Dbl]

class DecoupledIO[T <: Data] extends Bundle

class DecoupledIOC[+T <: Data] extends Bundle

class Delay extends Node

class DeqIO[T <: Data] extends DecoupledIO[T]

class DotBackend extends Backend

class EnqIO[T <: Data] extends DecoupledIO[T]

case class EnumParam(value: String, values: List[String]) extends Param[String] with Product with Serializable

class Extract extends Node

class FPGABackend extends VerilogBackend

class Flo extends Bits with Num[Flo]

class FloBackend extends Backend

trait IODirection extends AnyRef

class Literal extends Node

class LockingArbiter[T <: Data] extends LockingArbiterLike[T]

abstract class LockingArbiterLike[T <: Data] extends Module

class LockingRRArbiter[T <: Data] extends LockingArbiterLike[T]

class Log2 extends Node

class MapTester[+T <: Module] extends Tester[T]

class Mem[T <: Data] extends AccessTracker with VecLike[T]

abstract class MemAccess extends Node

class MemRead extends MemAccess

class MemReadWrite extends MemAccess

class MemSeqRead extends MemAccess

class MemWrite extends MemAccess

class ModularCppBackend extends CppBackend

abstract class Module extends AnyRef

class Mux extends Op

abstract class Node extends nameable

trait Num[T <: Data] extends AnyRef

class Op extends Node

abstract class Param[+T] extends AnyRef

class Pipe[T <: Data] extends Module

class Printf extends PrintfBase

class PrintfBase extends Node

class PutativeMemWrite extends Node with proc

class Queue[T <: Data] extends Module

class QueueIO[T <: Data] extends Bundle

class ROM[T <: Data] extends Vec[T]

class ROMRead[T <: Data] extends Node

class RRArbiter[T <: Data] extends LockingRRArbiter[T]

case class RangeParam(value: Int, min: Int, max: Int, step: Int = 1, log: Boolean = false) extends Param[Int] with Product with Serializable

class Reg extends Delay with proc

class SInt extends Bits with Num[SInt]

class Sprintf extends PrintfBase

class TestIO extends AnyRef

class Tester[+T <: Module] extends AnyRef

class UInt extends Bits with Num[UInt]

class ValidIO[+T <: Data] extends Bundle

case class ValueParam(value: Any) extends Param[Any] with Product with Serializable

class VcdBackend extends Backend

class Vec[T <: Data] extends Aggregate with VecLike[T] with Cloneable

trait VecLike[T <: Data] extends IndexedSeq[T]

class VecProc extends Node with proc

class VerilogBackend extends Backend

trait nameable extends AnyRef