VerilogBackend

Value Members

1. final def !=(arg0: AnyRef): Boolean

   Definition Classes

   AnyRef

2. final def !=(arg0: Any): Boolean

   Definition Classes

   Any

3. final def ##(): Int

   Definition Classes

   AnyRef → Any

4. final def ==(arg0: AnyRef): Boolean

   Definition Classes

   AnyRef

5. final def ==(arg0: Any): Boolean

   Definition Classes

   Any

6. val analyses: ArrayBuffer[(Module) ⇒ Unit]

   Definition Classes

   Backend

7. final def asInstanceOf[T0]: T0

   Definition Classes

   Any

8. def asValidName(name: String): String

   Definition Classes

   Backend

9. def assignClockAndResetToModules: Unit

   Definition Classes

   Backend

10. def backannotationAnalyses: Unit

    Definition Classes

    Backend

11. def backannotationTransforms: Unit

    Definition Classes

    Backend

12. def checkPorts(topC: Module): Unit

    Definition Classes

    Backend

13. def clone(): AnyRef

    Attributes

    protected[java.lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

14. def collectNodesIntoComp(dfsStack: Stack[Node]): Unit

    Definition Classes

    Backend

15. val compIndices: HashMap[String, Int]

16. def compile(c: Module, flags: String): Unit

    Definition Classes

    VerilogBackend → Backend

17. def connectResets: Unit

    Definition Classes

    Backend

18. def createOutputFile(name: String): FileWriter

    Definition Classes

    Backend

19. def depthString(depth: Int): String

    Definition Classes

    Backend

20. def doCompile(top: Module, out: FileWriter, depth: Int): Unit

21. def elaborate(c: Module): Unit

    Definition Classes

    VerilogBackend → Backend

22. def emitAssert(a: Assert): String

23. def emitChildren(top: Module, defs: LinkedHashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], out: FileWriter, depth: Int): Unit

24. def emitDec(node: Node): String

    Definition Classes

    VerilogBackend → Backend

25. def emitDecBase(node: Node): String

26. def emitDecs(c: Module): StringBuilder

27. def emitDef(node: Node): String

    Definition Classes

    VerilogBackend → Backend

28. def emitDef(c: Module): String

29. def emitDefs(c: Module): StringBuilder

30. def emitInit(node: Node): String

31. def emitInits(c: Module): StringBuilder

32. def emitModuleText(c: Module): String

33. def emitPortDef(m: MemAccess, idx: Int): String

34. def emitPrintf(p: Printf): String

35. def emitRef(node: Node): String

    Definition Classes

    VerilogBackend → Backend

36. def emitRef(c: Module): String

    Definition Classes

    Backend

37. def emitReg(node: Node): String

38. def emitRegs(c: Module): StringBuilder

39. def emitTmp(node: Node): String

    Definition Classes

    VerilogBackend → Backend

40. def emitWidth(node: Node): String

41. def ensureDir(dir: String): String

    Ensures a directory *dir* exists on the filesystem.

    Ensures a directory *dir* exists on the filesystem.

    Definition Classes

    Backend

42. final def eq(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef

43. def equals(arg0: Any): Boolean

    Definition Classes

    AnyRef → Any

44. def execute(c: Module, walks: ArrayBuffer[(Module) ⇒ Unit]): Unit

    Definition Classes

    Backend

45. def extractClassName(comp: Module): String

    Definition Classes

    Backend

46. def finalize(): Unit

    Attributes

    protected[java.lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( classOf[java.lang.Throwable] )

47. def flushModules(out: FileWriter, defs: LinkedHashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], level: Int): Unit

48. val flushedTexts: HashSet[String]

49. def fullyQualifiedName(m: Node): String

    Definition Classes

    Backend

50. def gatherChildren(root: Module): ArrayBuffer[Module]

    Definition Classes

    Backend

51. def gatherClocksAndResets: Unit

    Definition Classes

    Backend

52. def genHarness(c: Module, name: String): Unit

53. def genIndent(x: Int): String

    Attributes

    protected

    Definition Classes

    Backend

54. final def getClass(): Class[_]

    Definition Classes

    AnyRef → Any

55. def getPseudoPath(c: Module, delim: String = "/"): String

    Definition Classes

    Backend

56. def getSignalPathName(n: Node, delim: String = "/", isRealName: Boolean = false): String

    Definition Classes

    Backend

57. def hashCode(): Int

    Definition Classes

    AnyRef → Any

58. def initBackannotation: Unit

    Definition Classes

    Backend

59. def initializeDFS: Stack[Node]

    Definition Classes

    Backend

60. def isBitsIo(node: Node, dir: IODirection): Boolean

    Nodes which are created outside the execution trace from the toplevel component constructor (i.

    Nodes which are created outside the execution trace from the toplevel component constructor (i.e. through the () => Module(new Top()) ChiselMain argument) will have a component field set to null. For example, genMuxes, forceMatchWidths and transforms (all called from Backend.elaborate) create such nodes.

    This method walks all nodes from all component roots (outputs, debugs). and reassociates the component to the node both ways (i.e. in Driver.nodes and Node.component).

    We assume here that all nodes at the components boundaries (io) have a non-null and correct node/component association. We further assume that nodes generated in elaborate are inputs to a node whose component field is set.

    Implementation Node: At first we did implement *collectNodesIntoComp* to handle a single component at a time but that did not catch the cases where Regs are passed as input to sub-module without being tied to an output of *this.component*.

    Definition Classes

    Backend

61. def isEmittingComponents: Boolean

    Definition Classes

    VerilogBackend → Backend

62. final def isInstanceOf[T0]: Boolean

    Definition Classes

    Any

63. val keywords: HashSet[String]

    Definition Classes

    VerilogBackend → Backend

64. def levelChildren(root: Module): Unit

    Definition Classes

    Backend

65. val memConfs: HashMap[String, String]

66. def nameAll(root: Module): Unit

    Definition Classes

    Backend

67. def nameChildren(root: Module): Unit

    Definition Classes

    Backend

68. def nameRsts: Unit

    Definition Classes

    Backend

69. final def ne(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef

70. final def notify(): Unit

    Definition Classes

    AnyRef

71. final def notifyAll(): Unit

    Definition Classes

    AnyRef

72. val preElaborateTransforms: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes

    Backend

73. def printStack: Unit

    Prints the call stack of Component as seen by the push/pop runtime.

    Prints the call stack of Component as seen by the push/pop runtime.

    Attributes

    protected

    Definition Classes

    Backend

74. def pruneNodes: Unit

    Definition Classes

    Backend

75. def pruneUnconnectedIOs(m: Module): Unit

    Definition Classes

    Backend

76. def romStyle: String

77. def setPseudoNames(c: Module): Unit

    Definition Classes

    Backend

78. final def synchronized[T0](arg0: ⇒ T0): T0

    Definition Classes

    AnyRef

79. def toString(): String

    Definition Classes

    AnyRef → Any

80. val transforms: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes

    Backend

81. final def wait(): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

82. final def wait(arg0: Long, arg1: Int): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

83. final def wait(arg0: Long): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

84. def writeOutGraph(c: Module): Unit

    Definition Classes

    Backend