Driver

Value Members

final def !=(arg0: AnyRef): Boolean

Definition Classes
AnyRef
final def !=(arg0: Any): Boolean

Definition Classes
Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: AnyRef): Boolean

Definition Classes
AnyRef
final def ==(arg0: Any): Boolean

Definition Classes
Any
def apply[T <: Module](args: Array[String], gen: () ⇒ T, ftester: (T) ⇒ Tester[T]): T
def apply[T <: Module](args: Array[String], gen: () ⇒ T): T
final def asInstanceOf[T0]: T0

Definition Classes
Any
var backend: Backend
val blackboxes: ArrayBuffer[BlackBox]
val chiselOneHotBitMap: HashMap[(Bits, Int), Bool]
val chiselOneHotMap: HashMap[(UInt, Int), UInt]
val clocks: ArrayBuffer[Clock]
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( ... )
val compStack: Stack[Module]
val components: ArrayBuffer[Module]
var dontFindCombLoop: Boolean
var dumpTestInput: Boolean
def elapsedTime: Long
var emitTempNodes: Boolean
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
var getLineNumbers: Boolean
def hashCode(): Int

Definition Classes
AnyRef → Any
var implicitClock: Clock
var implicitReset: Bool
var includeArgs: List[String]
def initChisel(args: Array[String]): Unit
var isBackannotating: Boolean
var isCSE: Boolean
var isCheckingPorts: Boolean
var isCompiling: Boolean
var isDebug: Boolean
var isDebugMem: Boolean
var isGenHarness: Boolean
var isInGetWidth: Boolean
var isInlineMem: Boolean
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
var isIoDebug: Boolean
var isReportDims: Boolean
var isTesting: Boolean
var isVCD: Boolean
var isVCDMem: Boolean
var jackDir: String
var jackDump: String
var jackLoad: String
var jackN: Int
var modStackPushed: Boolean
var model: String
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
val nodes: ArrayBuffer[Node]
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
val printStackStruct: ArrayBuffer[(Int, Module)]
val pseudoMuxes: HashMap[Node, Node]
val randInitIOs: ArrayBuffer[Node]
var saveComponentTrace: Boolean
var saveConnectionWarnings: Boolean
def setTopComponent(mod: Module): Unit
val signals: LinkedHashSet[Node]
var sortedComps: ArrayBuffer[Module]
var stackIndent: Int
var startTime: Long
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
var targetDir: String
var testerSeed: Long
var testerSeedValid: Boolean
def toString(): String

Definition Classes
AnyRef → Any
var topComponent: Module
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
var warnInputs: Boolean
var warnOutputs: Boolean

object Driver

Value Members

final def !=(arg0: AnyRef): Boolean

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: AnyRef): Boolean

final def ==(arg0: Any): Boolean

def apply[T <: Module](args: Array[String], gen: () ⇒ T, ftester: (T) ⇒ Tester[T]): T

def apply[T <: Module](args: Array[String], gen: () ⇒ T): T

final def asInstanceOf[T0]: T0

var backend: Backend

val blackboxes: ArrayBuffer[BlackBox]

val chiselOneHotBitMap: HashMap[(Bits, Int), Bool]

val chiselOneHotMap: HashMap[(UInt, Int), UInt]

val clocks: ArrayBuffer[Clock]

def clone(): AnyRef

val compStack: Stack[Module]

val components: ArrayBuffer[Module]

var dontFindCombLoop: Boolean

var dumpTestInput: Boolean

def elapsedTime: Long

var emitTempNodes: Boolean

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

def finalize(): Unit

final def getClass(): Class[_]

var getLineNumbers: Boolean

def hashCode(): Int

var implicitClock: Clock

var implicitReset: Bool

var includeArgs: List[String]

def initChisel(args: Array[String]): Unit

var isBackannotating: Boolean

var isCSE: Boolean

var isCheckingPorts: Boolean

var isCompiling: Boolean

var isDebug: Boolean

var isDebugMem: Boolean

var isGenHarness: Boolean

var isInGetWidth: Boolean

var isInlineMem: Boolean

final def isInstanceOf[T0]: Boolean

var isIoDebug: Boolean

var isReportDims: Boolean

var isTesting: Boolean

var isVCD: Boolean

var isVCDMem: Boolean

var jackDir: String

var jackDump: String

var jackLoad: String

var jackN: Int

var modStackPushed: Boolean

var model: String

final def ne(arg0: AnyRef): Boolean

val nodes: ArrayBuffer[Node]

final def notify(): Unit

final def notifyAll(): Unit

val printStackStruct: ArrayBuffer[(Int, Module)]

val pseudoMuxes: HashMap[Node, Node]

val randInitIOs: ArrayBuffer[Node]

var saveComponentTrace: Boolean

var saveConnectionWarnings: Boolean

def setTopComponent(mod: Module): Unit

val signals: LinkedHashSet[Node]

var sortedComps: ArrayBuffer[Module]

var stackIndent: Int

var startTime: Long

final def synchronized[T0](arg0: ⇒ T0): T0

var targetDir: String

var testerSeed: Long

var testerSeedValid: Boolean

def toString(): String

var topComponent: Module

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

var warnInputs: Boolean

var warnOutputs: Boolean

Inherited from AnyRef