Fame1VerilogBackend

Value Members

1. final def !=(arg0: AnyRef): Boolean

   Definition Classes

   AnyRef

2. final def !=(arg0: Any): Boolean

   Definition Classes

   Any

3. final def ##(): Int

   Definition Classes

   AnyRef → Any

4. final def ==(arg0: AnyRef): Boolean

   Definition Classes

   AnyRef

5. final def ==(arg0: Any): Boolean

   Definition Classes

   Any

6. val analyses: ArrayBuffer[(Module) ⇒ Unit]

   Definition Classes

   Backend

7. final def asInstanceOf[T0]: T0

   Definition Classes

   Any

8. def asValidName(name: String): String

   Definition Classes

   Backend

9. def assignClockAndResetToModules: Unit

   Definition Classes

   Backend

10. def backannotationAnalyses: Unit

    Definition Classes

    Backend

11. def backannotationTransforms: Unit

    Definition Classes

    Backend

12. def checkPorts(topC: Module): Unit

    Definition Classes

    Backend

13. def clone(): AnyRef

    Attributes

    protected[java.lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

14. def collectNodesIntoComp(dfsStack: Stack[Node]): Unit

    Definition Classes

    Backend

15. val compIndices: HashMap[String, Int]

    Definition Classes

    VerilogBackend

16. def compile(c: Module, flags: String): Unit

    Definition Classes

    VerilogBackend → Backend

17. def connectResets: Unit

    Definition Classes

    Backend

18. def createOutputFile(name: String): FileWriter

    Definition Classes

    Backend

19. def depthString(depth: Int): String

    Definition Classes

    Backend

20. def doCompile(top: Module, out: FileWriter, depth: Int): Unit

    Definition Classes

    VerilogBackend

21. def elaborate(c: Module): Unit

    Definition Classes

    VerilogBackend → Backend

22. def emitAssert(a: Assert): String

    Definition Classes

    VerilogBackend

23. def emitChildren(top: Module, defs: LinkedHashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], out: FileWriter, depth: Int): Unit

    Definition Classes

    VerilogBackend

24. def emitDec(node: Node): String

    Definition Classes

    VerilogBackend → Backend

25. def emitDecBase(node: Node, wire: String = "wire"): String

    Definition Classes

    VerilogBackend

26. def emitDecReg(node: Node): String

    Definition Classes

    VerilogBackend

27. def emitDecs(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

28. def emitDef(node: Node): String

    Definition Classes

    VerilogBackend → Backend

29. def emitDef(c: Module): String

    Definition Classes

    VerilogBackend

30. def emitDefs(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

31. def emitInit(node: Node): String

    Definition Classes

    VerilogBackend

32. def emitInits(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

33. def emitModuleText(c: Module): String

    Definition Classes

    VerilogBackend

34. def emitPortDef(m: MemAccess, idx: Int): String

    Definition Classes

    VerilogBackend

35. def emitPrintf(p: Printf): String

    Definition Classes

    VerilogBackend

36. def emitRef(node: Node): String

    Definition Classes

    VerilogBackend → Backend

37. def emitRef(c: Module): String

    Definition Classes

    Backend

38. def emitReg(node: Node): String

    Definition Classes

    VerilogBackend

39. def emitRegs(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

40. def emitTmp(node: Node): String

    Definition Classes

    VerilogBackend → Backend

41. def emitWidth(node: Node): String

    Definition Classes

    VerilogBackend

42. def ensureDir(dir: String): String

    Ensures a directory *dir* exists on the filesystem.

    Ensures a directory *dir* exists on the filesystem.

    Definition Classes

    Backend

43. final def eq(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef

44. def equals(arg0: Any): Boolean

    Definition Classes

    AnyRef → Any

45. def execute(c: Module, walks: ArrayBuffer[(Module) ⇒ Unit]): Unit

    Definition Classes

    Backend

46. def extractClassName(comp: Module): String

    Definition Classes

    Backend

47. def finalize(): Unit

    Attributes

    protected[java.lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( classOf[java.lang.Throwable] )

48. def flushModules(out: FileWriter, defs: LinkedHashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], level: Int): Unit

    Definition Classes

    VerilogBackend

49. val flushedTexts: HashSet[String]

    Definition Classes

    VerilogBackend

50. def fullyQualifiedName(m: Node): String

    Definition Classes

    Backend

51. def gatherChildren(root: Module): ArrayBuffer[Module]

    Definition Classes

    Backend

52. def gatherClocksAndResets: Unit

    Definition Classes

    Backend

53. def genHarness(c: Module, name: String): Unit

    Definition Classes

    VerilogBackend

54. def genIndent(x: Int): String

    Attributes

    protected

    Definition Classes

    Backend

55. final def getClass(): Class[_]

    Definition Classes

    AnyRef → Any

56. def getPseudoPath(c: Module, delim: String = "/"): String

    Definition Classes

    Backend

57. def getSignalPathName(n: Node, delim: String = "/", isRealName: Boolean = false): String

    Definition Classes

    Backend

58. def harnessAPIs(mainClk: Clock, clocks: LinkedHashSet[Clock], resets: ArrayBuffer[Bool], wires: ArrayBuffer[Node], mems: ArrayBuffer[Mem[_]], scanNodes: Array[Bits], printNodes: Array[Bits]): String

    Definition Classes

    VerilogBackend

59. def harnessMap(mainClk: Clock, resets: ArrayBuffer[Bool], scanNodes: Array[Bits], printNodes: Array[Bits]): String

    * Test bench for replay **

    * Test bench for replay **

    Definition Classes

    VerilogBackend

60. def hashCode(): Int

    Definition Classes

    AnyRef → Any

61. def initBackannotation: Unit

    Definition Classes

    Backend

62. def initializeDFS: Stack[Node]

    Definition Classes

    Backend

63. def isBitsIo(node: Node, dir: IODirection): Boolean

    Nodes which are created outside the execution trace from the toplevel component constructor (i.

    Nodes which are created outside the execution trace from the toplevel component constructor (i.e. through the () => Module(new Top()) ChiselMain argument) will have a component field set to null. For example, genMuxes, forceMatchWidths and transforms (all called from Backend.elaborate) create such nodes.

    This method walks all nodes from all component roots (outputs, debugs). and reassociates the component to the node both ways (i.e. in Driver.nodes and Node.component).

    We assume here that all nodes at the components boundaries (io) have a non-null and correct node/component association. We further assume that nodes generated in elaborate are inputs to a node whose component field is set.

    Implementation Node: At first we did implement *collectNodesIntoComp* to handle a single component at a time but that did not catch the cases where Regs are passed as input to sub-module without being tied to an output of *this.component*.

    Definition Classes

    Backend

64. def isEmittingComponents: Boolean

    Definition Classes

    VerilogBackend → Backend

65. final def isInstanceOf[T0]: Boolean

    Definition Classes

    Any

66. val keywords: HashSet[String]

    Definition Classes

    VerilogBackend → Backend

67. def levelChildren(root: Module): Unit

    Definition Classes

    Backend

68. val memConfs: HashMap[String, String]

    Definition Classes

    VerilogBackend

69. def nameAll(root: Module): Unit

    Definition Classes

    Backend

70. def nameChildren(root: Module): Unit

    Definition Classes

    Backend

71. def nameRsts: Unit

    Definition Classes

    Backend

72. final def ne(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef

73. val needsLowering: Set[String]

    Definition Classes

    VerilogBackend → Backend

74. final def notify(): Unit

    Definition Classes

    AnyRef

75. final def notifyAll(): Unit

    Definition Classes

    AnyRef

76. val preElaborateTransforms: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes

    Backend

77. def printStack: Unit

    Prints the call stack of Component as seen by the push/pop runtime.

    Prints the call stack of Component as seen by the push/pop runtime.

    Attributes

    protected

    Definition Classes

    Backend

78. def pruneNodes: Unit

    Definition Classes

    Backend

79. def pruneUnconnectedIOs(m: Module): Unit

    Definition Classes

    Backend

80. def setPseudoNames(c: Module): Unit

    Definition Classes

    Backend

81. final def synchronized[T0](arg0: ⇒ T0): T0

    Definition Classes

    AnyRef

82. def toString(): String

    Definition Classes

    AnyRef → Any

83. val transforms: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes

    Backend

84. final def wait(): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

85. final def wait(arg0: Long, arg1: Int): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

86. final def wait(arg0: Long): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

87. def writeOutGraph(c: Module): Unit

    Definition Classes

    Backend