Fame1FPGABackend

Value Members

1. final def !=(arg0: AnyRef): Boolean

   Definition Classes

   AnyRef

2. final def !=(arg0: Any): Boolean

   Definition Classes

   Any

3. final def ##(): Int

   Definition Classes

   AnyRef → Any

4. final def ==(arg0: AnyRef): Boolean

   Definition Classes

   AnyRef

5. final def ==(arg0: Any): Boolean

   Definition Classes

   Any

6. val CC: String

   Attributes

   protected

   Definition Classes

   FileSystemUtilities

7. val CCFLAGS: String

   Attributes

   protected

   Definition Classes

   FileSystemUtilities

8. val CPPFLAGS: String

   Attributes

   protected

   Definition Classes

   FileSystemUtilities

9. val CXX: String

   Attributes

   protected

   Definition Classes

   FileSystemUtilities

10. val CXXFLAGS: String

    Attributes

    protected

    Definition Classes

    FileSystemUtilities

11. val LDFLAGS: String

    Attributes

    protected

    Definition Classes

    FileSystemUtilities

12. def W0Wtransform(): Unit

    Definition Classes

    Backend

13. def addBindings: Unit

    Definition Classes

    Backend

14. def addClocksAndResets: Unit

    Definition Classes

    Backend

15. def addDefaultResets: Unit

    Definition Classes

    Backend

16. val analyses: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes

    Backend

17. final def asInstanceOf[T0]: T0

    Definition Classes

    Any

18. def asValidName(name: String): String

    Definition Classes

    Backend

19. def assignClockAndResetToModules: Unit

    Definition Classes

    Backend

20. def cc(dir: String, name: String, flags: String = "", isCC: Boolean = false): Unit

    Definition Classes

    FileSystemUtilities

21. def checkModuleResolution: Unit

    Definition Classes

    Backend

22. def checkPorts: Unit

    Definition Classes

    Backend

23. val chiselENV: String

    Attributes

    protected

    Definition Classes

    FileSystemUtilities

24. def clone(): AnyRef

    Attributes

    protected[java.lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

25. def collectNodesIntoComp(mod: Module): Unit

    Definition Classes

    Backend

26. val compIndices: HashMap[String, Int]

    Definition Classes

    VerilogBackend

27. def compile(c: Module, flags: Option[String]): Unit

    Definition Classes

    VerilogBackend → Backend

28. def computeMemPorts(mod: Module): Unit

    Definition Classes

    Backend

29. def connectResets: Unit

    Definition Classes

    Backend

30. def convertMaskedWrites(mod: Module): Unit

    Definition Classes

    Backend

31. def copyToTarget(filename: String): Unit

    Definition Classes

    FileSystemUtilities

32. def createOutputFile(name: String): FileWriter

    Definition Classes

    FileSystemUtilities

33. def delimitUncommentedPortDecls(portDecls: ArrayBuffer[StringBuilder]): Unit

    Definition Classes

    VerilogBackend

34. def doCompile(top: Module, out: FileWriter, depth: Int): Unit

    Definition Classes

    VerilogBackend

35. def elaborate(c: Module): Unit

    Definition Classes

    VerilogBackend → Backend

36. def emitAssert(a: Assert): String

    Definition Classes

    VerilogBackend

37. def emitChildren(top: Module, defs: LinkedHashMap[String, LinkedHashMap[StringBuilder, ArrayBuffer[Module]]], out: FileWriter, depth: Int): Unit

    Definition Classes

    VerilogBackend

38. def emitDec(node: Node): String

    Definition Classes

    VerilogBackend → Backend

39. def emitDecBase(node: Node, wire: String = "wire"): String

    Definition Classes

    VerilogBackend

40. def emitDecReg(node: Node): String

    Definition Classes

    VerilogBackend

41. def emitDecs(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

42. def emitDef(node: Node): String

    Definition Classes

    VerilogBackend → Backend

43. def emitDef(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

44. def emitDefs(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

45. def emitInit(node: Node): String

    Definition Classes

    VerilogBackend

46. def emitInits(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

47. def emitModuleText(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

48. def emitPortDef(m: MemAccess, idx: Int): String

    Definition Classes

    VerilogBackend

49. def emitPrintf(p: Printf): String

    Definition Classes

    VerilogBackend

50. def emitRef(node: Node): String

    Definition Classes

    VerilogBackend → Backend

51. def emitRef(c: Module): String

    Definition Classes

    Backend

52. def emitReg(node: Node): String

    Definition Classes

    VerilogBackend

53. def emitRegs(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

54. def emitTmp(node: Node): String

    Definition Classes

    VerilogBackend → Backend

55. def emitWidth(node: Node): String

    Definition Classes

    VerilogBackend

56. val emittedModules: HashSet[String]

    Definition Classes

    VerilogBackend

57. def ensureDir(dir: String): String

    Ensures a directory *dir* exists on the filesystem.

    Ensures a directory *dir* exists on the filesystem.

    Definition Classes

    FileSystemUtilities

58. final def eq(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef

59. def equals(arg0: Any): Boolean

    Definition Classes

    AnyRef → Any

60. def execute(c: Module, walks: ArrayBuffer[(Module) ⇒ Unit]): Unit

    Definition Classes

    Backend

61. def extractClassName(comp: Module): String

    Definition Classes

    Backend

62. def finalize(): Unit

    Attributes

    protected[java.lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( classOf[java.lang.Throwable] )

63. def findCombLoop: Unit

    Definition Classes

    Backend

64. def findConsumers(mod: Module): Unit

    Definition Classes

    Backend

65. def findGraphDims: (Int, Int, Int)

    Definition Classes

    Backend

66. def flattenAll: Unit

    Definition Classes

    Backend

67. def flushModules(defs: LinkedHashMap[String, LinkedHashMap[StringBuilder, ArrayBuffer[Module]]], level: Int): Unit

    Definition Classes

    VerilogBackend

68. def forceMatchingWidths: Unit

    Definition Classes

    Backend

69. def fullyQualifiedName(m: Node): String

    Definition Classes

    Backend

70. def gatherClocksAndResets: Unit

    Definition Classes

    Backend

71. def genHarness(c: Module, name: String): Unit

    Definition Classes

    VerilogBackend

72. def genIndent(x: Int): String

    Prints the call stack of Component as seen by the push/pop runtime.

    Prints the call stack of Component as seen by the push/pop runtime.

    Attributes

    protected

    Definition Classes

    Backend

73. final def getClass(): Class[_]

    Definition Classes

    AnyRef → Any

74. def hashCode(): Int

    Definition Classes

    AnyRef → Any

75. def inferAll(mod: Module): Int

    Definition Classes

    Backend

76. def isBitsIo(node: Node, dir: IODirection): Boolean

    Nodes which are created outside the execution trace from the toplevel component constructor (i.

    Nodes which are created outside the execution trace from the toplevel component constructor (i.e. through the () => Module(new Top()) ChiselMain argument) will have a component field set to null. For example, genMuxes, forceMatchWidths and transforms (all called from Backend.elaborate) create such nodes.

    This method walks all nodes from all component roots (outputs, debugs). and reassociates the component to the node both ways (i.e. in Driver.nodes and Node.component).

    We assume here that all nodes at the components boundaries (io) have a non-null and correct node/component association. We further assume that nodes generated in elaborate are inputs to a node whose component field is set.

    Implementation Node: At first we did implement *collectNodesIntoComp* to handle a single component at a time but that did not catch the cases where Regs are passed as input to sub-module without being tied to an output of *this.component*.

    Definition Classes

    Backend

77. def isEmittingComponents: Boolean

    Definition Classes

    VerilogBackend → Backend

78. def isInObject(n: Node): Boolean

    Definition Classes

    Backend

79. final def isInstanceOf[T0]: Boolean

    Definition Classes

    Any

80. val keywords: Set[String]

    Definition Classes

    Backend

81. def link(dir: String, target: String, objects: Seq[String], isCC: Boolean = false, isLib: Boolean = false): Unit

    Definition Classes

    FileSystemUtilities

82. def lowerNodes(mod: Module): Unit

    Definition Classes

    Backend

83. def markComponents: Unit

    Definition Classes

    Backend

84. val memConfs: HashMap[String, String]

    Definition Classes

    VerilogBackend

85. def nameAll(): Unit

    Definition Classes

    Backend

86. def nameBindings: Unit

    Definition Classes

    Backend

87. def nameRsts: Unit

    Definition Classes

    Backend

88. val nameSpace: HashSet[String]

    Definition Classes

    Backend

89. final def ne(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef

90. val needsLowering: Set[String]

    Definition Classes

    VerilogBackend → Backend

91. final def notify(): Unit

    Definition Classes

    AnyRef

92. final def notifyAll(): Unit

    Definition Classes

    AnyRef

93. def printStack: Unit

    Attributes

    protected

    Definition Classes

    Backend

94. def pruneUnconnectedIOs: Unit

    Definition Classes

    Backend

95. def removeTypeNodes(mod: Module): Int

    All classes inherited from Data are used to add type information and do not represent logic itself.

    All classes inherited from Data are used to add type information and do not represent logic itself.

    Definition Classes

    Backend

96. def renameNodes(nodes: Seq[Node], sep: String = "_"): Unit

    Ensures each node such that it has a unique name across the whole hierarchy by prefixing its name by a component path (except for "reset" and all nodes in *c*).

    Ensures each node such that it has a unique name across the whole hierarchy by prefixing its name by a component path (except for "reset" and all nodes in *c*).

    Definition Classes

    Backend

97. def run(cmd: String): Boolean

    Definition Classes

    FileSystemUtilities

98. def sortComponents: Unit

    Definition Classes

    Backend

99. final def synchronized[T0](arg0: ⇒ T0): T0

    Definition Classes

    AnyRef

100. def synthesizeable(node: Node): Boolean

     Definition Classes

     VerilogBackend

101. def toString(): String

     Definition Classes

     AnyRef → Any

102. def topMod: Module

     Definition Classes

     Backend

103. val transforms: ArrayBuffer[(Module) ⇒ Unit]

     Definition Classes

     Backend

104. def verifyAllMuxes: Unit

     Definition Classes

     Backend

105. def verifyComponents: Unit

     Definition Classes

     Backend

106. final def wait(): Unit

     Definition Classes

     AnyRef

     Annotations

     @throws( ... )

107. final def wait(arg0: Long, arg1: Int): Unit

     Definition Classes

     AnyRef

     Annotations

     @throws( ... )

108. final def wait(arg0: Long): Unit

     Definition Classes

     AnyRef

     Annotations

     @throws( ... )