Chisel

VerilogParameters

class VerilogParameters extends AnyRef

This class enables the definition of verilog parameters without having to to string building

Source
hcl.scala
Example: 

  1. class MyParams extends VerilogParameters {
val MY_STR_PARAM = "FOO_BAR"
val MY_INT_PARAM = 3
val MY_BOOL_PARAM = true
}

    This will generate a string

    #(
.MY_STR_PARAM("FOO_BAR"),
.MY_INT_PARAM(3),
.MY_BOOL_PARAM(TRUE)
)

    Set these parameters with

    setVerilogParameters(new MyParams)

    inside a BlackBox module or use 

    setVerilogParameters(myCustomString)
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Instance Constructors

  1. new VerilogParameters()

Value Members

  1. final def !=(arg0: AnyRef): Boolean

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  2. final def !=(arg0: Any): Boolean

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  3. final def ##(): Int

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  4. final def ==(arg0: AnyRef): Boolean

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  5. final def ==(arg0: Any): Boolean

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  6. final def asInstanceOf[T0]: T0

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  7. def clone(): AnyRef

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  8. final def eq(arg0: AnyRef): Boolean

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  9. def equals(arg0: Any): Boolean

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  10. def finalize(): Unit

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  11. final def getClass(): Class[_]

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  12. def hashCode(): Int

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  13. final def isInstanceOf[T0]: Boolean

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  14. final def ne(arg0: AnyRef): Boolean

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  15. final def notify(): Unit

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  16. final def notifyAll(): Unit

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  17. final def synchronized[T0](arg0: ⇒ T0): T0

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  18. def toString(): String

    Get the string of verilog parameters

    Get the string of verilog parameters

    Definition Classes
    VerilogParameters → AnyRef → Any

  19. final def wait(): Unit

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    @throws( ... )

  20. final def wait(arg0: Long, arg1: Int): Unit

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  21. final def wait(arg0: Long): Unit

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