BlackBox

abstract def io: Data

final def !=(arg0: AnyRef): Boolean

final def !=(arg0: Any): Boolean

final def ##(): Int

def <>(src: Module): Unit

final def ==(arg0: AnyRef): Boolean

final def ==(arg0: Any): Boolean

def addClock(clock: Clock): Unit

def addClockAndReset: Unit

def addDefaultReset: Unit

def addResetPin(reset: Bool): Unit

def apply(name: String): Data

final def asInstanceOf[T0]: T0

def assert(cond: Bool, message: String): Unit

Add an assertion in the code generated by a backend.

def bfs(visit: (Node) ⇒ Unit): Unit

val bindings: ArrayBuffer[Binding]

val children: ArrayBuffer[Module]

var clock: Clock

val clocks: ArrayBuffer[Clock]

def clone(): AnyRef

def collectNodes(c: Module): Unit

var containsReg: Boolean

def containsRegInTree: Boolean

Returns true if this module or any of its children contains at least one register.

def debug(x: Node): Unit

Insures a backend does not remove a signal because it is unreachable from the outputs.

val debugs: HashSet[Node]

var defaultResetPin: Bool

var defaultWidth: Int

def depthString(depth: Int): String

def elaborate(fake: Int = 0): Unit

def emitDec(b: Backend): String

final def eq(arg0: AnyRef): Boolean

def equals(that: Any): Boolean

def finalize(): Unit

def findBinding(m: Node): Binding

def findCombLoop(): Unit

def findConsumers(): Unit

def findGraphDims(): (Int, Int, Int)

def findOrdering(): Unit

def findRoots(): ArrayBuffer[Node]

Since we are relying on the out-degree of nodes (i.

def forceMatchingWidths: Unit

def genAllMuxes: Unit

final def getClass(): Class[_]

def getClassValNames(c: Class[_]): ArrayBuffer[String]

def getPathName(separator: String = "_"): String

def getPathName: String

Returns the absolute path to a component instance from toplevel.

def getResetPin(reset: Bool): Bool

def getValNames: ArrayBuffer[String]

def hasClock: Boolean

var hasExplicitClock: Boolean

var hasExplicitReset: Boolean

def hasReset: Boolean

def hasWhenCond: Boolean

val hashCode: Int

def inferAll(): Int

def initializeBFS: scala.collection.mutable.Queue[Node]

def initializeDFS: Stack[Node]

var ioVal: Data

def isInferenceTerminal(m: Node): Boolean

def isInput(node: Node): Boolean

final def isInstanceOf[T0]: Boolean

def isSubclassOf(x: Class[_]): Boolean

object isValName

var isWalked: HashSet[Node]

var isWalking: HashSet[Node]

def keepInputs(nodes: Seq[Node]): Seq[Node]

var level: Int

A backend(Backend.

def markComponent(): Unit

val mods: ArrayBuffer[Node]

var moduleName: String

Name of the module this component generates (defaults to class name).

var name: String

Name of the instance.

var named: Boolean

val names: HashMap[String, Node]

final def ne(arg0: AnyRef): Boolean

def nextIndex: Int

val nexts: scala.collection.mutable.Queue[Node]

var nindex: Int

val nodes: ArrayBuffer[Node]

final def notify(): Unit

final def notifyAll(): Unit

val omods: ArrayBuffer[Node]

def ownIo(): Unit

var parent: Module

var pathParent: Module

def postMarkNet(fake: Int = 0): Unit

def printf(message: String, args: Node*): Unit

val regs: ArrayBuffer[Reg]

def removeInputs(nodes: Seq[Node]): Seq[Node]

def removeTypeNodes(): Int

All classes inherited from Data are used to add type information and do not represent logic itself.

def reset: Bool

def reset_=(): Unit

def reset_=(r: Bool): Unit

val resets: HashMap[Bool, Bool]

def setName(name: String): Unit

def setVerilogParameters(string: String): Unit

def stripComponent(s: String): String

val switchKeys: Stack[Bits]

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

def traceNodes(): Unit

def traceableNodes: Array[Node]

var traversal: Int

def verifyAllMuxes: Unit

var verilog_parameters: String

def visitNodes(roots: Array[Node]): Unit

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

def whenCond: Bool

val whenConds: Stack[Bool]

def wires: Array[(String, Bits)]

var wiresCache: Array[(String, Bits)]